Use upstream unicorn for Ryujinx.Tests.Unicorn (#3771)

* unicorn: Add modified ver of unicorns const gen

* unicorn: Use upstream consts

These consts were generated from the dev branch of unicorn

* unicorn: Split common consts into multiple enums

* unicorn: Remove arch prefix from consts

* unicorn: Add new windows dll

Windows 10 - MSVC x64 shared build

* unicorn: Use absolute path for const generation

* unicorn: Remove fspcr patch

* unicorn: Fix using the wrong file extension

For some reason _NativeLibraryExtension evaluates to ".so" even on Windows.

* unicorn: Add linux shared object again

* unicron: Add DllImportResolver

* unicorn: Try to import unicorn using an absolute path

* unicorn: Add clean target

* unicorn: Replace IsUnicornAvailable() methods

* unicorn: Skip tests instead of silently passing them if unicorn is missing

* unicorn: Write error message to stderr

* unicorn: Make Interface static

* unicron: Include prefixed unicorn libs (libunicorn.so)

Co-authored-by: merry <git@mary.rs>

* unicorn: Add lib prefix to shared object for linux

Co-authored-by: merry <git@mary.rs>

15 files changed, 795 insertions, 493 deletions

diff --git a/Ryujinx.Tests.Unicorn/Native/Arm32Register.cs b/Ryujinx.Tests.Unicorn/Native/Arm32Register.cs
deleted file mode 100644
index 419f8e4d..00000000
--- a/Ryujinx.Tests.Unicorn/Native/Arm32Register.cs
+++ /dev/null
@@ -1,135 +0,0 @@
-namespace Ryujinx.Tests.Unicorn.Native
-{
-    public enum Arm32Register
-    {
-        INVALID = 0,
-
-        APSR,
-        APSR_NZCV,
-        CPSR,
-        FPEXC,
-        FPINST,
-        FPSCR,
-        FPSCR_NZCV,
-        FPSID,
-        ITSTATE,
-        LR,
-        PC,
-        SP,
-        SPSR,
-        D0,
-        D1,
-        D2,
-        D3,
-        D4,
-        D5,
-        D6,
-        D7,
-        D8,
-        D9,
-        D10,
-        D11,
-        D12,
-        D13,
-        D14,
-        D15,
-        D16,
-        D17,
-        D18,
-        D19,
-        D20,
-        D21,
-        D22,
-        D23,
-        D24,
-        D25,
-        D26,
-        D27,
-        D28,
-        D29,
-        D30,
-        D31,
-        FPINST2,
-        MVFR0,
-        MVFR1,
-        MVFR2,
-        Q0,
-        Q1,
-        Q2,
-        Q3,
-        Q4,
-        Q5,
-        Q6,
-        Q7,
-        Q8,
-        Q9,
-        Q10,
-        Q11,
-        Q12,
-        Q13,
-        Q14,
-        Q15,
-        R0,
-        R1,
-        R2,
-        R3,
-        R4,
-        R5,
-        R6,
-        R7,
-        R8,
-        R9,
-        R10,
-        R11,
-        R12,
-        S0,
-        S1,
-        S2,
-        S3,
-        S4,
-        S5,
-        S6,
-        S7,
-        S8,
-        S9,
-        S10,
-        S11,
-        S12,
-        S13,
-        S14,
-        S15,
-        S16,
-        S17,
-        S18,
-        S19,
-        S20,
-        S21,
-        S22,
-        S23,
-        S24,
-        S25,
-        S26,
-        S27,
-        S28,
-        S29,
-        S30,
-        S31,
-        C1_C0_2,
-        C13_C0_2,
-        C13_C0_3,
-        IPSR,
-        MSP,
-        PSP,
-        CONTROL,
-        ENDING,
-
-        // Alias registers.
-        R13 = SP,
-        R14 = LR,
-        R15 = PC,
-        SB = R9,
-        SL = R10,
-        FP = R11,
-        IP = R12,
-    }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs b/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs
deleted file mode 100644
index af331bd1..00000000
--- a/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs
+++ /dev/null
@@ -1,295 +0,0 @@
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native
-{
-    public enum ArmRegister
-    {
-        INVALID = 0,
-
-        X29,
-        X30,
-        NZCV,
-        SP,
-        WSP,
-        WZR,
-        XZR,
-        B0,
-        B1,
-        B2,
-        B3,
-        B4,
-        B5,
-        B6,
-        B7,
-        B8,
-        B9,
-        B10,
-        B11,
-        B12,
-        B13,
-        B14,
-        B15,
-        B16,
-        B17,
-        B18,
-        B19,
-        B20,
-        B21,
-        B22,
-        B23,
-        B24,
-        B25,
-        B26,
-        B27,
-        B28,
-        B29,
-        B30,
-        B31,
-        D0,
-        D1,
-        D2,
-        D3,
-        D4,
-        D5,
-        D6,
-        D7,
-        D8,
-        D9,
-        D10,
-        D11,
-        D12,
-        D13,
-        D14,
-        D15,
-        D16,
-        D17,
-        D18,
-        D19,
-        D20,
-        D21,
-        D22,
-        D23,
-        D24,
-        D25,
-        D26,
-        D27,
-        D28,
-        D29,
-        D30,
-        D31,
-        H0,
-        H1,
-        H2,
-        H3,
-        H4,
-        H5,
-        H6,
-        H7,
-        H8,
-        H9,
-        H10,
-        H11,
-        H12,
-        H13,
-        H14,
-        H15,
-        H16,
-        H17,
-        H18,
-        H19,
-        H20,
-        H21,
-        H22,
-        H23,
-        H24,
-        H25,
-        H26,
-        H27,
-        H28,
-        H29,
-        H30,
-        H31,
-        Q0,
-        Q1,
-        Q2,
-        Q3,
-        Q4,
-        Q5,
-        Q6,
-        Q7,
-        Q8,
-        Q9,
-        Q10,
-        Q11,
-        Q12,
-        Q13,
-        Q14,
-        Q15,
-        Q16,
-        Q17,
-        Q18,
-        Q19,
-        Q20,
-        Q21,
-        Q22,
-        Q23,
-        Q24,
-        Q25,
-        Q26,
-        Q27,
-        Q28,
-        Q29,
-        Q30,
-        Q31,
-        S0,
-        S1,
-        S2,
-        S3,
-        S4,
-        S5,
-        S6,
-        S7,
-        S8,
-        S9,
-        S10,
-        S11,
-        S12,
-        S13,
-        S14,
-        S15,
-        S16,
-        S17,
-        S18,
-        S19,
-        S20,
-        S21,
-        S22,
-        S23,
-        S24,
-        S25,
-        S26,
-        S27,
-        S28,
-        S29,
-        S30,
-        S31,
-        W0,
-        W1,
-        W2,
-        W3,
-        W4,
-        W5,
-        W6,
-        W7,
-        W8,
-        W9,
-        W10,
-        W11,
-        W12,
-        W13,
-        W14,
-        W15,
-        W16,
-        W17,
-        W18,
-        W19,
-        W20,
-        W21,
-        W22,
-        W23,
-        W24,
-        W25,
-        W26,
-        W27,
-        W28,
-        W29,
-        W30,
-        X0,
-        X1,
-        X2,
-        X3,
-        X4,
-        X5,
-        X6,
-        X7,
-        X8,
-        X9,
-        X10,
-        X11,
-        X12,
-        X13,
-        X14,
-        X15,
-        X16,
-        X17,
-        X18,
-        X19,
-        X20,
-        X21,
-        X22,
-        X23,
-        X24,
-        X25,
-        X26,
-        X27,
-        X28,
-
-        V0,
-        V1,
-        V2,
-        V3,
-        V4,
-        V5,
-        V6,
-        V7,
-        V8,
-        V9,
-        V10,
-        V11,
-        V12,
-        V13,
-        V14,
-        V15,
-        V16,
-        V17,
-        V18,
-        V19,
-        V20,
-        V21,
-        V22,
-        V23,
-        V24,
-        V25,
-        V26,
-        V27,
-        V28,
-        V29,
-        V30,
-        V31,
-
-        // > pseudo registers
-        PC,            // program counter register
-
-        CPACR_EL1,
-        ESR,
-
-        // > thread registers
-        TPIDR_EL0,
-        TPIDRRO_EL0,
-        TPIDR_EL1,
-
-        PSTATE,        // PSTATE pseudoregister
-
-        // > floating point control and status registers
-        FPCR,
-        FPSR,
-
-        ENDING,        // <-- mark the end of the list of registers
-
-        // > alias registers
-
-        IP0 =   X16,
-        IP1 =   X17,
-        FP =    X29,
-        LR =    X30,
-    }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs
new file mode 100644
index 00000000..f614d091
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Arch.cs
@@ -0,0 +1,20 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Arch
+    {
+        ARM = 1,
+        ARM64 = 2,
+        MIPS = 3,
+        X86 = 4,
+        PPC = 5,
+        SPARC = 6,
+        M68K = 7,
+        RISCV = 8,
+        S390X = 9,
+        TRICORE = 10,
+        MAX = 11,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs
new file mode 100644
index 00000000..4b7b3d6f
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Arm.cs
@@ -0,0 +1,200 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Arm
+    {
+
+        // ARM CPU
+
+        CPU_ARM_926 = 0,
+        CPU_ARM_946 = 1,
+        CPU_ARM_1026 = 2,
+        CPU_ARM_1136_R2 = 3,
+        CPU_ARM_1136 = 4,
+        CPU_ARM_1176 = 5,
+        CPU_ARM_11MPCORE = 6,
+        CPU_ARM_CORTEX_M0 = 7,
+        CPU_ARM_CORTEX_M3 = 8,
+        CPU_ARM_CORTEX_M4 = 9,
+        CPU_ARM_CORTEX_M7 = 10,
+        CPU_ARM_CORTEX_M33 = 11,
+        CPU_ARM_CORTEX_R5 = 12,
+        CPU_ARM_CORTEX_R5F = 13,
+        CPU_ARM_CORTEX_A7 = 14,
+        CPU_ARM_CORTEX_A8 = 15,
+        CPU_ARM_CORTEX_A9 = 16,
+        CPU_ARM_CORTEX_A15 = 17,
+        CPU_ARM_TI925T = 18,
+        CPU_ARM_SA1100 = 19,
+        CPU_ARM_SA1110 = 20,
+        CPU_ARM_PXA250 = 21,
+        CPU_ARM_PXA255 = 22,
+        CPU_ARM_PXA260 = 23,
+        CPU_ARM_PXA261 = 24,
+        CPU_ARM_PXA262 = 25,
+        CPU_ARM_PXA270 = 26,
+        CPU_ARM_PXA270A0 = 27,
+        CPU_ARM_PXA270A1 = 28,
+        CPU_ARM_PXA270B0 = 29,
+        CPU_ARM_PXA270B1 = 30,
+        CPU_ARM_PXA270C0 = 31,
+        CPU_ARM_PXA270C5 = 32,
+        CPU_ARM_MAX = 33,
+        CPU_ARM_ENDING = 34,
+
+        // ARM registers
+
+        REG_INVALID = 0,
+        REG_APSR = 1,
+        REG_APSR_NZCV = 2,
+        REG_CPSR = 3,
+        REG_FPEXC = 4,
+        REG_FPINST = 5,
+        REG_FPSCR = 6,
+        REG_FPSCR_NZCV = 7,
+        REG_FPSID = 8,
+        REG_ITSTATE = 9,
+        REG_LR = 10,
+        REG_PC = 11,
+        REG_SP = 12,
+        REG_SPSR = 13,
+        REG_D0 = 14,
+        REG_D1 = 15,
+        REG_D2 = 16,
+        REG_D3 = 17,
+        REG_D4 = 18,
+        REG_D5 = 19,
+        REG_D6 = 20,
+        REG_D7 = 21,
+        REG_D8 = 22,
+        REG_D9 = 23,
+        REG_D10 = 24,
+        REG_D11 = 25,
+        REG_D12 = 26,
+        REG_D13 = 27,
+        REG_D14 = 28,
+        REG_D15 = 29,
+        REG_D16 = 30,
+        REG_D17 = 31,
+        REG_D18 = 32,
+        REG_D19 = 33,
+        REG_D20 = 34,
+        REG_D21 = 35,
+        REG_D22 = 36,
+        REG_D23 = 37,
+        REG_D24 = 38,
+        REG_D25 = 39,
+        REG_D26 = 40,
+        REG_D27 = 41,
+        REG_D28 = 42,
+        REG_D29 = 43,
+        REG_D30 = 44,
+        REG_D31 = 45,
+        REG_FPINST2 = 46,
+        REG_MVFR0 = 47,
+        REG_MVFR1 = 48,
+        REG_MVFR2 = 49,
+        REG_Q0 = 50,
+        REG_Q1 = 51,
+        REG_Q2 = 52,
+        REG_Q3 = 53,
+        REG_Q4 = 54,
+        REG_Q5 = 55,
+        REG_Q6 = 56,
+        REG_Q7 = 57,
+        REG_Q8 = 58,
+        REG_Q9 = 59,
+        REG_Q10 = 60,
+        REG_Q11 = 61,
+        REG_Q12 = 62,
+        REG_Q13 = 63,
+        REG_Q14 = 64,
+        REG_Q15 = 65,
+        REG_R0 = 66,
+        REG_R1 = 67,
+        REG_R2 = 68,
+        REG_R3 = 69,
+        REG_R4 = 70,
+        REG_R5 = 71,
+        REG_R6 = 72,
+        REG_R7 = 73,
+        REG_R8 = 74,
+        REG_R9 = 75,
+        REG_R10 = 76,
+        REG_R11 = 77,
+        REG_R12 = 78,
+        REG_S0 = 79,
+        REG_S1 = 80,
+        REG_S2 = 81,
+        REG_S3 = 82,
+        REG_S4 = 83,
+        REG_S5 = 84,
+        REG_S6 = 85,
+        REG_S7 = 86,
+        REG_S8 = 87,
+        REG_S9 = 88,
+        REG_S10 = 89,
+        REG_S11 = 90,
+        REG_S12 = 91,
+        REG_S13 = 92,
+        REG_S14 = 93,
+        REG_S15 = 94,
+        REG_S16 = 95,
+        REG_S17 = 96,
+        REG_S18 = 97,
+        REG_S19 = 98,
+        REG_S20 = 99,
+        REG_S21 = 100,
+        REG_S22 = 101,
+        REG_S23 = 102,
+        REG_S24 = 103,
+        REG_S25 = 104,
+        REG_S26 = 105,
+        REG_S27 = 106,
+        REG_S28 = 107,
+        REG_S29 = 108,
+        REG_S30 = 109,
+        REG_S31 = 110,
+        REG_C1_C0_2 = 111,
+        REG_C13_C0_2 = 112,
+        REG_C13_C0_3 = 113,
+        REG_IPSR = 114,
+        REG_MSP = 115,
+        REG_PSP = 116,
+        REG_CONTROL = 117,
+        REG_IAPSR = 118,
+        REG_EAPSR = 119,
+        REG_XPSR = 120,
+        REG_EPSR = 121,
+        REG_IEPSR = 122,
+        REG_PRIMASK = 123,
+        REG_BASEPRI = 124,
+        REG_BASEPRI_MAX = 125,
+        REG_FAULTMASK = 126,
+        REG_APSR_NZCVQ = 127,
+        REG_APSR_G = 128,
+        REG_APSR_NZCVQG = 129,
+        REG_IAPSR_NZCVQ = 130,
+        REG_IAPSR_G = 131,
+        REG_IAPSR_NZCVQG = 132,
+        REG_EAPSR_NZCVQ = 133,
+        REG_EAPSR_G = 134,
+        REG_EAPSR_NZCVQG = 135,
+        REG_XPSR_NZCVQ = 136,
+        REG_XPSR_G = 137,
+        REG_XPSR_NZCVQG = 138,
+        REG_CP_REG = 139,
+        REG_ENDING = 140,
+
+        // alias registers
+        REG_R13 = 12,
+        REG_R14 = 10,
+        REG_R15 = 11,
+        REG_SB = 75,
+        REG_SL = 76,
+        REG_FP = 77,
+        REG_IP = 78,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs b/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs
new file mode 100644
index 00000000..11344557
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Arm64.cs
@@ -0,0 +1,341 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Arm64
+    {
+
+        // ARM64 CPU
+
+        CPU_ARM64_A57 = 0,
+        CPU_ARM64_A53 = 1,
+        CPU_ARM64_A72 = 2,
+        CPU_ARM64_MAX = 3,
+        CPU_ARM64_ENDING = 4,
+
+        // ARM64 registers
+
+        REG_INVALID = 0,
+        REG_X29 = 1,
+        REG_X30 = 2,
+        REG_NZCV = 3,
+        REG_SP = 4,
+        REG_WSP = 5,
+        REG_WZR = 6,
+        REG_XZR = 7,
+        REG_B0 = 8,
+        REG_B1 = 9,
+        REG_B2 = 10,
+        REG_B3 = 11,
+        REG_B4 = 12,
+        REG_B5 = 13,
+        REG_B6 = 14,
+        REG_B7 = 15,
+        REG_B8 = 16,
+        REG_B9 = 17,
+        REG_B10 = 18,
+        REG_B11 = 19,
+        REG_B12 = 20,
+        REG_B13 = 21,
+        REG_B14 = 22,
+        REG_B15 = 23,
+        REG_B16 = 24,
+        REG_B17 = 25,
+        REG_B18 = 26,
+        REG_B19 = 27,
+        REG_B20 = 28,
+        REG_B21 = 29,
+        REG_B22 = 30,
+        REG_B23 = 31,
+        REG_B24 = 32,
+        REG_B25 = 33,
+        REG_B26 = 34,
+        REG_B27 = 35,
+        REG_B28 = 36,
+        REG_B29 = 37,
+        REG_B30 = 38,
+        REG_B31 = 39,
+        REG_D0 = 40,
+        REG_D1 = 41,
+        REG_D2 = 42,
+        REG_D3 = 43,
+        REG_D4 = 44,
+        REG_D5 = 45,
+        REG_D6 = 46,
+        REG_D7 = 47,
+        REG_D8 = 48,
+        REG_D9 = 49,
+        REG_D10 = 50,
+        REG_D11 = 51,
+        REG_D12 = 52,
+        REG_D13 = 53,
+        REG_D14 = 54,
+        REG_D15 = 55,
+        REG_D16 = 56,
+        REG_D17 = 57,
+        REG_D18 = 58,
+        REG_D19 = 59,
+        REG_D20 = 60,
+        REG_D21 = 61,
+        REG_D22 = 62,
+        REG_D23 = 63,
+        REG_D24 = 64,
+        REG_D25 = 65,
+        REG_D26 = 66,
+        REG_D27 = 67,
+        REG_D28 = 68,
+        REG_D29 = 69,
+        REG_D30 = 70,
+        REG_D31 = 71,
+        REG_H0 = 72,
+        REG_H1 = 73,
+        REG_H2 = 74,
+        REG_H3 = 75,
+        REG_H4 = 76,
+        REG_H5 = 77,
+        REG_H6 = 78,
+        REG_H7 = 79,
+        REG_H8 = 80,
+        REG_H9 = 81,
+        REG_H10 = 82,
+        REG_H11 = 83,
+        REG_H12 = 84,
+        REG_H13 = 85,
+        REG_H14 = 86,
+        REG_H15 = 87,
+        REG_H16 = 88,
+        REG_H17 = 89,
+        REG_H18 = 90,
+        REG_H19 = 91,
+        REG_H20 = 92,
+        REG_H21 = 93,
+        REG_H22 = 94,
+        REG_H23 = 95,
+        REG_H24 = 96,
+        REG_H25 = 97,
+        REG_H26 = 98,
+        REG_H27 = 99,
+        REG_H28 = 100,
+        REG_H29 = 101,
+        REG_H30 = 102,
+        REG_H31 = 103,
+        REG_Q0 = 104,
+        REG_Q1 = 105,
+        REG_Q2 = 106,
+        REG_Q3 = 107,
+        REG_Q4 = 108,
+        REG_Q5 = 109,
+        REG_Q6 = 110,
+        REG_Q7 = 111,
+        REG_Q8 = 112,
+        REG_Q9 = 113,
+        REG_Q10 = 114,
+        REG_Q11 = 115,
+        REG_Q12 = 116,
+        REG_Q13 = 117,
+        REG_Q14 = 118,
+        REG_Q15 = 119,
+        REG_Q16 = 120,
+        REG_Q17 = 121,
+        REG_Q18 = 122,
+        REG_Q19 = 123,
+        REG_Q20 = 124,
+        REG_Q21 = 125,
+        REG_Q22 = 126,
+        REG_Q23 = 127,
+        REG_Q24 = 128,
+        REG_Q25 = 129,
+        REG_Q26 = 130,
+        REG_Q27 = 131,
+        REG_Q28 = 132,
+        REG_Q29 = 133,
+        REG_Q30 = 134,
+        REG_Q31 = 135,
+        REG_S0 = 136,
+        REG_S1 = 137,
+        REG_S2 = 138,
+        REG_S3 = 139,
+        REG_S4 = 140,
+        REG_S5 = 141,
+        REG_S6 = 142,
+        REG_S7 = 143,
+        REG_S8 = 144,
+        REG_S9 = 145,
+        REG_S10 = 146,
+        REG_S11 = 147,
+        REG_S12 = 148,
+        REG_S13 = 149,
+        REG_S14 = 150,
+        REG_S15 = 151,
+        REG_S16 = 152,
+        REG_S17 = 153,
+        REG_S18 = 154,
+        REG_S19 = 155,
+        REG_S20 = 156,
+        REG_S21 = 157,
+        REG_S22 = 158,
+        REG_S23 = 159,
+        REG_S24 = 160,
+        REG_S25 = 161,
+        REG_S26 = 162,
+        REG_S27 = 163,
+        REG_S28 = 164,
+        REG_S29 = 165,
+        REG_S30 = 166,
+        REG_S31 = 167,
+        REG_W0 = 168,
+        REG_W1 = 169,
+        REG_W2 = 170,
+        REG_W3 = 171,
+        REG_W4 = 172,
+        REG_W5 = 173,
+        REG_W6 = 174,
+        REG_W7 = 175,
+        REG_W8 = 176,
+        REG_W9 = 177,
+        REG_W10 = 178,
+        REG_W11 = 179,
+        REG_W12 = 180,
+        REG_W13 = 181,
+        REG_W14 = 182,
+        REG_W15 = 183,
+        REG_W16 = 184,
+        REG_W17 = 185,
+        REG_W18 = 186,
+        REG_W19 = 187,
+        REG_W20 = 188,
+        REG_W21 = 189,
+        REG_W22 = 190,
+        REG_W23 = 191,
+        REG_W24 = 192,
+        REG_W25 = 193,
+        REG_W26 = 194,
+        REG_W27 = 195,
+        REG_W28 = 196,
+        REG_W29 = 197,
+        REG_W30 = 198,
+        REG_X0 = 199,
+        REG_X1 = 200,
+        REG_X2 = 201,
+        REG_X3 = 202,
+        REG_X4 = 203,
+        REG_X5 = 204,
+        REG_X6 = 205,
+        REG_X7 = 206,
+        REG_X8 = 207,
+        REG_X9 = 208,
+        REG_X10 = 209,
+        REG_X11 = 210,
+        REG_X12 = 211,
+        REG_X13 = 212,
+        REG_X14 = 213,
+        REG_X15 = 214,
+        REG_X16 = 215,
+        REG_X17 = 216,
+        REG_X18 = 217,
+        REG_X19 = 218,
+        REG_X20 = 219,
+        REG_X21 = 220,
+        REG_X22 = 221,
+        REG_X23 = 222,
+        REG_X24 = 223,
+        REG_X25 = 224,
+        REG_X26 = 225,
+        REG_X27 = 226,
+        REG_X28 = 227,
+        REG_V0 = 228,
+        REG_V1 = 229,
+        REG_V2 = 230,
+        REG_V3 = 231,
+        REG_V4 = 232,
+        REG_V5 = 233,
+        REG_V6 = 234,
+        REG_V7 = 235,
+        REG_V8 = 236,
+        REG_V9 = 237,
+        REG_V10 = 238,
+        REG_V11 = 239,
+        REG_V12 = 240,
+        REG_V13 = 241,
+        REG_V14 = 242,
+        REG_V15 = 243,
+        REG_V16 = 244,
+        REG_V17 = 245,
+        REG_V18 = 246,
+        REG_V19 = 247,
+        REG_V20 = 248,
+        REG_V21 = 249,
+        REG_V22 = 250,
+        REG_V23 = 251,
+        REG_V24 = 252,
+        REG_V25 = 253,
+        REG_V26 = 254,
+        REG_V27 = 255,
+        REG_V28 = 256,
+        REG_V29 = 257,
+        REG_V30 = 258,
+        REG_V31 = 259,
+
+        // pseudo registers
+        REG_PC = 260,
+        REG_CPACR_EL1 = 261,
+
+        // thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
+        REG_TPIDR_EL0 = 262,
+        REG_TPIDRRO_EL0 = 263,
+        REG_TPIDR_EL1 = 264,
+        REG_PSTATE = 265,
+
+        // exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
+        REG_ELR_EL0 = 266,
+        REG_ELR_EL1 = 267,
+        REG_ELR_EL2 = 268,
+        REG_ELR_EL3 = 269,
+
+        // stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
+        REG_SP_EL0 = 270,
+        REG_SP_EL1 = 271,
+        REG_SP_EL2 = 272,
+        REG_SP_EL3 = 273,
+
+        // other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
+        REG_TTBR0_EL1 = 274,
+        REG_TTBR1_EL1 = 275,
+        REG_ESR_EL0 = 276,
+        REG_ESR_EL1 = 277,
+        REG_ESR_EL2 = 278,
+        REG_ESR_EL3 = 279,
+        REG_FAR_EL0 = 280,
+        REG_FAR_EL1 = 281,
+        REG_FAR_EL2 = 282,
+        REG_FAR_EL3 = 283,
+        REG_PAR_EL1 = 284,
+        REG_MAIR_EL1 = 285,
+        REG_VBAR_EL0 = 286,
+        REG_VBAR_EL1 = 287,
+        REG_VBAR_EL2 = 288,
+        REG_VBAR_EL3 = 289,
+        REG_CP_REG = 290,
+
+        // floating point control and status registers
+        REG_FPCR = 291,
+        REG_FPSR = 292,
+        REG_ENDING = 293,
+
+        // alias registers
+        REG_IP0 = 215,
+        REG_IP1 = 216,
+        REG_FP = 1,
+        REG_LR = 2,
+
+        // ARM64 instructions
+
+        INS_INVALID = 0,
+        INS_MRS = 1,
+        INS_MSR = 2,
+        INS_SYS = 3,
+        INS_SYSL = 4,
+        INS_ENDING = 5,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Common.cs b/Ryujinx.Tests.Unicorn/Native/Const/Common.cs
new file mode 100644
index 00000000..e4b59a48
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Common.cs
@@ -0,0 +1,44 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Common
+    {
+        API_MAJOR = 2,
+
+        API_MINOR = 0,
+
+        API_PATCH = 0,
+        API_EXTRA = 255,
+        VERSION_MAJOR = 2,
+
+        VERSION_MINOR = 0,
+
+        VERSION_PATCH = 0,
+        VERSION_EXTRA = 255,
+        SECOND_SCALE = 1000000,
+        MILISECOND_SCALE = 1000,
+        QUERY_MODE = 1,
+        QUERY_PAGE_SIZE = 2,
+        QUERY_ARCH = 3,
+        QUERY_TIMEOUT = 4,
+
+        CTL_IO_NONE = 0,
+        CTL_IO_WRITE = 1,
+        CTL_IO_READ = 2,
+        CTL_IO_READ_WRITE = 3,
+
+        CTL_UC_MODE = 0,
+        CTL_UC_PAGE_SIZE = 1,
+        CTL_UC_ARCH = 2,
+        CTL_UC_TIMEOUT = 3,
+        CTL_UC_USE_EXITS = 4,
+        CTL_UC_EXITS_CNT = 5,
+        CTL_UC_EXITS = 6,
+        CTL_CPU_MODEL = 7,
+        CTL_TB_REQUEST_CACHE = 8,
+        CTL_TB_REMOVE_CACHE = 9,
+        CTL_TB_FLUSH = 10,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Error.cs b/Ryujinx.Tests.Unicorn/Native/Const/Error.cs
new file mode 100644
index 00000000..9cedb0fc
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Error.cs
@@ -0,0 +1,31 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Error
+    {
+        OK = 0,
+        NOMEM = 1,
+        ARCH = 2,
+        HANDLE = 3,
+        MODE = 4,
+        VERSION = 5,
+        READ_UNMAPPED = 6,
+        WRITE_UNMAPPED = 7,
+        FETCH_UNMAPPED = 8,
+        HOOK = 9,
+        INSN_INVALID = 10,
+        MAP = 11,
+        WRITE_PROT = 12,
+        READ_PROT = 13,
+        FETCH_PROT = 14,
+        ARG = 15,
+        READ_UNALIGNED = 16,
+        WRITE_UNALIGNED = 17,
+        FETCH_UNALIGNED = 18,
+        HOOK_EXIST = 19,
+        RESOURCE = 20,
+        EXCEPTION = 21,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs b/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs
new file mode 100644
index 00000000..a6b9dca6
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Hook.cs
@@ -0,0 +1,33 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Hook
+    {
+        INTR = 1,
+        INSN = 2,
+        CODE = 4,
+        BLOCK = 8,
+        MEM_READ_UNMAPPED = 16,
+        MEM_WRITE_UNMAPPED = 32,
+        MEM_FETCH_UNMAPPED = 64,
+        MEM_READ_PROT = 128,
+        MEM_WRITE_PROT = 256,
+        MEM_FETCH_PROT = 512,
+        MEM_READ = 1024,
+        MEM_WRITE = 2048,
+        MEM_FETCH = 4096,
+        MEM_READ_AFTER = 8192,
+        INSN_INVALID = 16384,
+        EDGE_GENERATED = 32768,
+        TCG_OPCODE = 65536,
+        MEM_UNMAPPED = 112,
+        MEM_PROT = 896,
+        MEM_READ_INVALID = 144,
+        MEM_WRITE_INVALID = 288,
+        MEM_FETCH_INVALID = 576,
+        MEM_INVALID = 1008,
+        MEM_VALID = 7168,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs b/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs
new file mode 100644
index 00000000..a7d60e61
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Memory.cs
@@ -0,0 +1,19 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Memory
+    {
+        READ = 16,
+        WRITE = 17,
+        FETCH = 18,
+        READ_UNMAPPED = 19,
+        WRITE_UNMAPPED = 20,
+        FETCH_UNMAPPED = 21,
+        WRITE_PROT = 22,
+        READ_PROT = 23,
+        FETCH_PROT = 24,
+        READ_AFTER = 25,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs b/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs
new file mode 100644
index 00000000..804d01a9
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Mode.cs
@@ -0,0 +1,35 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Mode
+    {
+        LITTLE_ENDIAN = 0,
+        BIG_ENDIAN = 1073741824,
+        ARM = 0,
+        THUMB = 16,
+        MCLASS = 32,
+        V8 = 64,
+        ARMBE8 = 1024,
+        ARM926 = 128,
+        ARM946 = 256,
+        ARM1176 = 512,
+        MICRO = 16,
+        MIPS3 = 32,
+        MIPS32R6 = 64,
+        MIPS32 = 4,
+        MIPS64 = 8,
+        MODE_16 = 2,
+        MODE_32 = 4,
+        MODE_64 = 8,
+        PPC32 = 4,
+        PPC64 = 8,
+        QPX = 16,
+        SPARC32 = 4,
+        SPARC64 = 8,
+        V9 = 16,
+        RISCV32 = 4,
+        RISCV64 = 8,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs b/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs
new file mode 100644
index 00000000..19ddc4f2
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/Permission.cs
@@ -0,0 +1,14 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum Permission
+    {
+        NONE = 0,
+        READ = 1,
+        WRITE = 2,
+        EXEC = 4,
+        ALL = 7,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs b/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs
new file mode 100644
index 00000000..f38785db
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Const/TCG.cs
@@ -0,0 +1,12 @@
+// Constants for Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+// ReSharper disable InconsistentNaming
+namespace Ryujinx.Tests.Unicorn.Native.Const
+{
+    public enum TCG
+    {
+        OP_SUB = 0,
+        OP_FLAG_CMP = 1,
+        OP_FLAG_DIRECT = 2,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Interface.cs b/Ryujinx.Tests.Unicorn/Native/Interface.cs
index 59b1da07..0ecda22e 100644
--- a/Ryujinx.Tests.Unicorn/Native/Interface.cs
+++ b/Ryujinx.Tests.Unicorn/Native/Interface.cs
@@ -1,13 +1,43 @@
+using Ryujinx.Tests.Unicorn.Native.Const;
 using System;
+using System.IO;
+using System.Reflection;
 using System.Runtime.InteropServices;
 
 namespace Ryujinx.Tests.Unicorn.Native
 {
-    public class Interface
+    public static class Interface
     {
-        public static void Checked(UnicornError error)
+        public static bool IsUnicornAvailable { get; private set; } = true;
+
+        private static IntPtr ImportResolver(string libraryName, Assembly assembly, DllImportSearchPath? searchPath)
+        {
+            if (libraryName == "unicorn")
+            {
+                string loadPath = $"{Path.GetDirectoryName(assembly.Location)}/";
+                loadPath += OperatingSystem.IsWindows() ? $"{libraryName}.dll" : $"lib{libraryName}.so";
+
+                if (!NativeLibrary.TryLoad(loadPath, out IntPtr libraryPtr))
+                {
+                    IsUnicornAvailable = false;
+                    Console.Error.WriteLine($"ERROR: Could not find unicorn at: {loadPath}");
+                }
+
+                return libraryPtr;
+            }
+
+            // Otherwise, fallback to default import resolver.
+            return IntPtr.Zero;
+        }
+
+        static Interface()
+        {
+            NativeLibrary.SetDllImportResolver(Assembly.GetExecutingAssembly(), ImportResolver);
+        }
+
+        public static void Checked(Error error)
         {
-            if (error != UnicornError.UC_ERR_OK)
+            if (error != Error.OK)
             {
                 throw new UnicornException(error);
             }
@@ -31,39 +61,39 @@ namespace Ryujinx.Tests.Unicorn.Native
         public static extern uint uc_version(out uint major, out uint minor);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_open(UnicornArch arch, UnicornMode mode, out IntPtr uc);
+        public static extern Error uc_open(Arch arch, Mode mode, out IntPtr uc);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_close(IntPtr uc);
+        public static extern Error uc_close(IntPtr uc);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern IntPtr uc_strerror(UnicornError err);
+        public static extern IntPtr uc_strerror(Error err);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_reg_write(IntPtr uc, int regid, byte[] value);
+        public static extern Error uc_reg_write(IntPtr uc, int regid, byte[] value);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_reg_read(IntPtr uc, int regid, byte[] value);
+        public static extern Error uc_reg_read(IntPtr uc, int regid, byte[] value);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_write(IntPtr uc, ulong address, byte[] bytes, ulong size);
+        public static extern Error uc_mem_write(IntPtr uc, ulong address, byte[] bytes, ulong size);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_read(IntPtr uc, ulong address, byte[] bytes, ulong size);
+        public static extern Error uc_mem_read(IntPtr uc, ulong address, byte[] bytes, ulong size);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_emu_start(IntPtr uc, ulong begin, ulong until, ulong timeout, ulong count);
+        public static extern Error uc_emu_start(IntPtr uc, ulong begin, ulong until, ulong timeout, ulong count);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_map(IntPtr uc, ulong address, ulong size, uint perms);
+        public static extern Error uc_mem_map(IntPtr uc, ulong address, ulong size, uint perms);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_unmap(IntPtr uc, ulong address, ulong size);
+        public static extern Error uc_mem_unmap(IntPtr uc, ulong address, ulong size);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_protect(IntPtr uc, ulong address, ulong size, uint perms);
+        public static extern Error uc_mem_protect(IntPtr uc, ulong address, ulong size, uint perms);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_mem_regions(IntPtr uc, out IntPtr regions, out uint count);
+        public static extern Error uc_mem_regions(IntPtr uc, out IntPtr regions, out uint count);
     }
-}
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs b/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
deleted file mode 100644
index ff633293..00000000
--- a/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
+++ /dev/null
@@ -1,14 +0,0 @@
-namespace Ryujinx.Tests.Unicorn.Native
-{
-    public enum UnicornArch : uint
-    {
-        UC_ARCH_ARM = 1,    // ARM architecture (including Thumb, Thumb-2)
-        UC_ARCH_ARM64,      // ARM-64, also called AArch64
-        UC_ARCH_MIPS,       // Mips architecture
-        UC_ARCH_X86,        // X86 architecture (including x86 & x86-64)
-        UC_ARCH_PPC,        // PowerPC architecture (currently unsupported)
-        UC_ARCH_SPARC,      // Sparc architecture
-        UC_ARCH_M68K,       // M68K architecture
-        UC_ARCH_MAX,
-    }
-}
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs b/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
deleted file mode 100644
index 8045f2da..00000000
--- a/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
+++ /dev/null
@@ -1,33 +0,0 @@
-// ReSharper disable InconsistentNaming
-namespace Ryujinx.Tests.Unicorn.Native
-{
-    public enum UnicornMode : uint
-    {
-        UC_MODE_LITTLE_ENDIAN = 0,    // little-endian mode (default mode)
-        UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
-        // arm / arm64
-        UC_MODE_ARM = 0,              // ARM mode
-        UC_MODE_THUMB = 1 << 4,       // THUMB mode (including Thumb-2)
-        UC_MODE_MCLASS = 1 << 5,      // ARM's Cortex-M series (currently unsupported)
-        UC_MODE_V8 = 1 << 6,          // ARMv8 A32 encodings for ARM (currently unsupported)
-        // mips
-        UC_MODE_MICRO = 1 << 4,       // MicroMips mode (currently unsupported)
-        UC_MODE_MIPS3 = 1 << 5,       // Mips III ISA (currently unsupported)
-        UC_MODE_MIPS32R6 = 1 << 6,    // Mips32r6 ISA (currently unsupported)
-        UC_MODE_MIPS32 = 1 << 2,      // Mips32 ISA
-        UC_MODE_MIPS64 = 1 << 3,      // Mips64 ISA
-        // x86 / x64
-        UC_MODE_16 = 1 << 1,          // 16-bit mode
-        UC_MODE_32 = 1 << 2,          // 32-bit mode
-        UC_MODE_64 = 1 << 3,          // 64-bit mode
-        // ppc
-        UC_MODE_PPC32 = 1 << 2,       // 32-bit mode (currently unsupported)
-        UC_MODE_PPC64 = 1 << 3,       // 64-bit mode (currently unsupported)
-        UC_MODE_QPX = 1 << 4,         // Quad Processing eXtensions mode (currently unsupported)
-        // sparc
-        UC_MODE_SPARC32 = 1 << 2,     // 32-bit mode
-        UC_MODE_SPARC64 = 1 << 3,     // 64-bit mode
-        UC_MODE_V9 = 1 << 4,          // SparcV9 mode (currently unsupported)
-        // m68k
-    }
-}