Ryujinx.Tests: Add unicorn to test framework (#389)

* Ryujinx.Tests: Add unicorn to test framework

* CpuTestSimdArithmetic: Comment out inaccurate results

5 files changed, 427 insertions, 0 deletions

diff --git a/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs b/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs
new file mode 100644
index 00000000..3554480c
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/ArmRegister.cs
@@ -0,0 +1,296 @@
+using System;
+
+namespace Ryujinx.Tests.Unicorn.Native
+{
+    public enum ArmRegister
+    {
+        INVALID = 0,
+
+        X29,
+        X30,
+        NZCV,
+        SP,
+        WSP,
+        WZR,
+        XZR,
+        B0,
+        B1,
+        B2,
+        B3,
+        B4,
+        B5,
+        B6,
+        B7,
+        B8,
+        B9,
+        B10,
+        B11,
+        B12,
+        B13,
+        B14,
+        B15,
+        B16,
+        B17,
+        B18,
+        B19,
+        B20,
+        B21,
+        B22,
+        B23,
+        B24,
+        B25,
+        B26,
+        B27,
+        B28,
+        B29,
+        B30,
+        B31,
+        D0,
+        D1,
+        D2,
+        D3,
+        D4,
+        D5,
+        D6,
+        D7,
+        D8,
+        D9,
+        D10,
+        D11,
+        D12,
+        D13,
+        D14,
+        D15,
+        D16,
+        D17,
+        D18,
+        D19,
+        D20,
+        D21,
+        D22,
+        D23,
+        D24,
+        D25,
+        D26,
+        D27,
+        D28,
+        D29,
+        D30,
+        D31,
+        H0,
+        H1,
+        H2,
+        H3,
+        H4,
+        H5,
+        H6,
+        H7,
+        H8,
+        H9,
+        H10,
+        H11,
+        H12,
+        H13,
+        H14,
+        H15,
+        H16,
+        H17,
+        H18,
+        H19,
+        H20,
+        H21,
+        H22,
+        H23,
+        H24,
+        H25,
+        H26,
+        H27,
+        H28,
+        H29,
+        H30,
+        H31,
+        Q0,
+        Q1,
+        Q2,
+        Q3,
+        Q4,
+        Q5,
+        Q6,
+        Q7,
+        Q8,
+        Q9,
+        Q10,
+        Q11,
+        Q12,
+        Q13,
+        Q14,
+        Q15,
+        Q16,
+        Q17,
+        Q18,
+        Q19,
+        Q20,
+        Q21,
+        Q22,
+        Q23,
+        Q24,
+        Q25,
+        Q26,
+        Q27,
+        Q28,
+        Q29,
+        Q30,
+        Q31,
+        S0,
+        S1,
+        S2,
+        S3,
+        S4,
+        S5,
+        S6,
+        S7,
+        S8,
+        S9,
+        S10,
+        S11,
+        S12,
+        S13,
+        S14,
+        S15,
+        S16,
+        S17,
+        S18,
+        S19,
+        S20,
+        S21,
+        S22,
+        S23,
+        S24,
+        S25,
+        S26,
+        S27,
+        S28,
+        S29,
+        S30,
+        S31,
+        W0,
+        W1,
+        W2,
+        W3,
+        W4,
+        W5,
+        W6,
+        W7,
+        W8,
+        W9,
+        W10,
+        W11,
+        W12,
+        W13,
+        W14,
+        W15,
+        W16,
+        W17,
+        W18,
+        W19,
+        W20,
+        W21,
+        W22,
+        W23,
+        W24,
+        W25,
+        W26,
+        W27,
+        W28,
+        W29,
+        W30,
+        X0,
+        X1,
+        X2,
+        X3,
+        X4,
+        X5,
+        X6,
+        X7,
+        X8,
+        X9,
+        X10,
+        X11,
+        X12,
+        X13,
+        X14,
+        X15,
+        X16,
+        X17,
+        X18,
+        X19,
+        X20,
+        X21,
+        X22,
+        X23,
+        X24,
+        X25,
+        X26,
+        X27,
+        X28,
+
+        V0,
+        V1,
+        V2,
+        V3,
+        V4,
+        V5,
+        V6,
+        V7,
+        V8,
+        V9,
+        V10,
+        V11,
+        V12,
+        V13,
+        V14,
+        V15,
+        V16,
+        V17,
+        V18,
+        V19,
+        V20,
+        V21,
+        V22,
+        V23,
+        V24,
+        V25,
+        V26,
+        V27,
+        V28,
+        V29,
+        V30,
+        V31,
+
+        //> pseudo registers
+        PC,            // program counter register
+
+        CPACR_EL1,
+        ESR,
+
+        //> thread registers
+        TPIDR_EL0,
+        TPIDRRO_EL0,
+        TPIDR_EL1,
+
+        PSTATE,        // PSTATE pseudoregister
+
+        //> floating point control and status registers
+        FPCR,
+        FPSR,
+
+        ENDING,        // <-- mark the end of the list of registers
+
+        //> alias registers
+
+        IP0 =   X16,
+        IP1 =   X17,
+        FP =    X29,
+        LR =    X30,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/Interface.cs b/Ryujinx.Tests.Unicorn/Native/Interface.cs
new file mode 100644
index 00000000..a6563220
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/Interface.cs
@@ -0,0 +1,68 @@
+using System;
+using System.Runtime.InteropServices;
+using Ryujinx.Tests.Unicorn;
+
+namespace Ryujinx.Tests.Unicorn.Native
+{
+    public class Interface
+    {
+        public static void Checked(UnicornError error)
+        {
+            if (error != UnicornError.UC_ERR_OK)
+            {
+                throw new UnicornException(error);
+            }
+        }
+
+        public static void MarshalArrayOf<T>(IntPtr input, int length, out T[] output)
+        {
+            var size = Marshal.SizeOf(typeof(T));
+            output = new T[length];
+
+            for (int i = 0; i < length; i++)
+            {
+                IntPtr item = new IntPtr(input.ToInt64() + i * size);
+                output[i] = Marshal.PtrToStructure<T>(item);
+            }
+         }
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern uint uc_version(out uint major, out uint minor);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_open(uint arch, uint mode, out IntPtr uc);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_close(IntPtr uc);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern IntPtr uc_strerror(UnicornError err);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_reg_write(IntPtr uc, int regid, byte[] value);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_reg_read(IntPtr uc, int regid, byte[] value);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_write(IntPtr uc, ulong address, byte[] bytes, ulong size);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_read(IntPtr uc, ulong address, byte[] bytes, ulong size);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_emu_start(IntPtr uc, ulong begin, ulong until, ulong timeout, ulong count);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_map(IntPtr uc, ulong address, ulong size, uint perms);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_unmap(IntPtr uc, ulong address, ulong size);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_protect(IntPtr uc, ulong address, ulong size, uint perms);
+
+        [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
+        public static extern UnicornError uc_mem_regions(IntPtr uc, out IntPtr regions, out uint count);
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs b/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
new file mode 100644
index 00000000..be088366
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
@@ -0,0 +1,16 @@
+using System;
+
+namespace Ryujinx.Tests.Unicorn.Native
+{
+    public enum UnicornArch
+    {
+        UC_ARCH_ARM = 1,    // ARM architecture (including Thumb, Thumb-2)
+        UC_ARCH_ARM64,      // ARM-64, also called AArch64
+        UC_ARCH_MIPS,       // Mips architecture
+        UC_ARCH_X86,        // X86 architecture (including x86 & x86-64)
+        UC_ARCH_PPC,        // PowerPC architecture (currently unsupported)
+        UC_ARCH_SPARC,      // Sparc architecture
+        UC_ARCH_M68K,       // M68K architecture
+        UC_ARCH_MAX,
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs b/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs
new file mode 100644
index 00000000..7ee34a74
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/UnicornMemoryRegion.cs
@@ -0,0 +1,13 @@
+using System;
+using System.Runtime.InteropServices;
+
+namespace Ryujinx.Tests.Unicorn.Native
+{
+    [StructLayout(LayoutKind.Sequential)]
+    public struct UnicornMemoryRegion
+    {
+        public UInt64 begin; // begin address of the region (inclusive)
+        public UInt64 end;   // end address of the region (inclusive)
+        public UInt32 perms; // memory permissions of the region
+    }
+}
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs b/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
new file mode 100644
index 00000000..950583bd
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
@@ -0,0 +1,34 @@
+using System;
+
+namespace Ryujinx.Tests.Unicorn.Native
+{
+    public enum UnicornMode
+    {
+        UC_MODE_LITTLE_ENDIAN = 0,    // little-endian mode (default mode)
+        UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
+        // arm / arm64
+        UC_MODE_ARM = 0,              // ARM mode
+        UC_MODE_THUMB = 1 << 4,       // THUMB mode (including Thumb-2)
+        UC_MODE_MCLASS = 1 << 5,      // ARM's Cortex-M series (currently unsupported)
+        UC_MODE_V8 = 1 << 6,          // ARMv8 A32 encodings for ARM (currently unsupported)
+        // mips
+        UC_MODE_MICRO = 1 << 4,       // MicroMips mode (currently unsupported)
+        UC_MODE_MIPS3 = 1 << 5,       // Mips III ISA (currently unsupported)
+        UC_MODE_MIPS32R6 = 1 << 6,    // Mips32r6 ISA (currently unsupported)
+        UC_MODE_MIPS32 = 1 << 2,      // Mips32 ISA
+        UC_MODE_MIPS64 = 1 << 3,      // Mips64 ISA
+        // x86 / x64
+        UC_MODE_16 = 1 << 1,          // 16-bit mode
+        UC_MODE_32 = 1 << 2,          // 32-bit mode
+        UC_MODE_64 = 1 << 3,          // 64-bit mode
+        // ppc
+        UC_MODE_PPC32 = 1 << 2,       // 32-bit mode (currently unsupported)
+        UC_MODE_PPC64 = 1 << 3,       // 64-bit mode (currently unsupported)
+        UC_MODE_QPX = 1 << 4,         // Quad Processing eXtensions mode (currently unsupported)
+        // sparc
+        UC_MODE_SPARC32 = 1 << 2,     // 32-bit mode
+        UC_MODE_SPARC64 = 1 << 3,     // 64-bit mode
+        UC_MODE_V9 = 1 << 4,          // SparcV9 mode (currently unsupported)
+        // m68k
+    }
+}