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authorgdkchan <gab.dark.100@gmail.com>2019-04-17 20:57:08 -0300
committerjduncanator <1518948+jduncanator@users.noreply.github.com>2019-04-18 09:57:08 +1000
commit6b23a2c125b9c48b5ebea92716004ef68698bb0f (patch)
tree69332df6fbbd8e2bddc522ba682fcc5c7a69e101 /Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs
parentb2e88b04a85b41cc60af3485d88c90429e84a218 (diff)
New shader translator implementation (#654)
* Start implementing a new shader translator * Fix shift instructions and a typo * Small refactoring on StructuredProgram, move RemovePhis method to a separate class * Initial geometry shader support * Implement TLD4 * Fix -- There's no negation on FMUL32I * Add constant folding and algebraic simplification optimizations, nits * Some leftovers from constant folding * Avoid cast for constant assignments * Add a branch elimination pass, and misc small fixes * Remove redundant branches, add expression propagation and other improvements on the code * Small leftovers -- add missing break and continue, remove unused properties, other improvements * Add null check to handle empty block cases on block visitor * Add HADD2 and HMUL2 half float shader instructions * Optimize pack/unpack sequences, some fixes related to half float instructions * Add TXQ, TLD, TLDS and TLD4S shader texture instructions, and some support for bindless textures, some refactoring on codegen * Fix copy paste mistake that caused RZ to be ignored on the AST instruction * Add workaround for conditional exit, and fix half float instruction with constant buffer * Add missing 0.0 source for TLDS.LZ variants * Simplify the switch for TLDS.LZ * Texture instructions related fixes * Implement the HFMA instruction, and some misc. fixes * Enable constant folding on UnpackHalf2x16 instructions * Refactor HFMA to use OpCode* for opcode decoding rather than on the helper methods * Remove the old shader translator * Remove ShaderDeclInfo and other unused things * Add dual vertex shader support * Add ShaderConfig, used to pass shader type and maximum cbuffer size * Move and rename some instruction enums * Move texture instructions into a separate file * Move operand GetExpression and locals management to OperandManager * Optimize opcode decoding using a simple list and binary search * Add missing condition for do-while on goto elimination * Misc. fixes on texture instructions * Simplify TLDS switch * Address PR feedback, and a nit
Diffstat (limited to 'Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs')
-rw-r--r--Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs138
1 files changed, 138 insertions, 0 deletions
diff --git a/Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs b/Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs
new file mode 100644
index 00000000..d81e97a1
--- /dev/null
+++ b/Ryujinx.Graphics/Shader/Instructions/InstEmitMemory.cs
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+using Ryujinx.Graphics.Shader.Decoders;
+using Ryujinx.Graphics.Shader.IntermediateRepresentation;
+using Ryujinx.Graphics.Shader.Translation;
+
+using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
+using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
+
+namespace Ryujinx.Graphics.Shader.Instructions
+{
+ static partial class InstEmit
+ {
+ public static void Ald(EmitterContext context)
+ {
+ OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
+
+ Operand[] elems = new Operand[op.Count];
+
+ for (int index = 0; index < op.Count; index++)
+ {
+ Operand src = Attribute(op.AttributeOffset + index * 4);
+
+ context.Copy(elems[index] = Local(), src);
+ }
+
+ for (int index = 0; index < op.Count; index++)
+ {
+ Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
+
+ if (rd.IsRZ)
+ {
+ break;
+ }
+
+ context.Copy(Register(rd), elems[index]);
+ }
+ }
+
+ public static void Ast(EmitterContext context)
+ {
+ OpCodeAttribute op = (OpCodeAttribute)context.CurrOp;
+
+ for (int index = 0; index < op.Count; index++)
+ {
+ if (op.Rd.Index + index > RegisterConsts.RegisterZeroIndex)
+ {
+ break;
+ }
+
+ Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
+
+ Operand dest = Attribute(op.AttributeOffset + index * 4);
+
+ context.Copy(dest, Register(rd));
+ }
+ }
+
+ public static void Ipa(EmitterContext context)
+ {
+ OpCodeIpa op = (OpCodeIpa)context.CurrOp;
+
+ Operand srcA = new Operand(OperandType.Attribute, op.AttributeOffset);
+
+ Operand srcB = GetSrcB(context);
+
+ context.Copy(GetDest(context), srcA);
+ }
+
+ public static void Ldc(EmitterContext context)
+ {
+ OpCodeLdc op = (OpCodeLdc)context.CurrOp;
+
+ if (op.Size > IntegerSize.B64)
+ {
+ //TODO: Warning.
+ }
+
+ bool isSmallInt = op.Size < IntegerSize.B32;
+
+ int count = op.Size == IntegerSize.B64 ? 2 : 1;
+
+ Operand baseOffset = context.Copy(GetSrcA(context));
+
+ for (int index = 0; index < count; index++)
+ {
+ Register rd = new Register(op.Rd.Index + index, RegisterType.Gpr);
+
+ if (rd.IsRZ)
+ {
+ break;
+ }
+
+ Operand offset = context.IAdd(baseOffset, Const((op.Offset + index) * 4));
+
+ Operand value = context.LoadConstant(Const(op.Slot), offset);
+
+ if (isSmallInt)
+ {
+ Operand shift = context.BitwiseAnd(baseOffset, Const(3));
+
+ value = context.ShiftRightU32(value, shift);
+
+ switch (op.Size)
+ {
+ case IntegerSize.U8: value = ZeroExtendTo32(context, value, 8); break;
+ case IntegerSize.U16: value = ZeroExtendTo32(context, value, 16); break;
+ case IntegerSize.S8: value = SignExtendTo32(context, value, 8); break;
+ case IntegerSize.S16: value = SignExtendTo32(context, value, 16); break;
+ }
+ }
+
+ context.Copy(Register(rd), value);
+ }
+ }
+
+ public static void Out(EmitterContext context)
+ {
+ OpCode op = context.CurrOp;
+
+ bool emit = op.RawOpCode.Extract(39);
+ bool cut = op.RawOpCode.Extract(40);
+
+ if (!(emit || cut))
+ {
+ //TODO: Warning.
+ }
+
+ if (emit)
+ {
+ context.EmitVertex();
+ }
+
+ if (cut)
+ {
+ context.EndPrimitive();
+ }
+ }
+ }
+} \ No newline at end of file