diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2020-10-21 09:13:44 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-21 09:13:44 -0300 |
| commit | 2f164917126ecef3a44c989e9442d2c663e58535 (patch) | |
| tree | b3a37b665bcebfe5c93108992a97fe90512f88dc /Ryujinx.Graphics.Shader | |
| parent | efa77a241555efa3ddfa3425919211ce6c8134a7 (diff) | |
Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)
* Get rid of Reflection.Emit dependency on CPU and Shader projects
* Remove useless private sets
* Missed those due to the alignment
Diffstat (limited to 'Ryujinx.Graphics.Shader')
63 files changed, 331 insertions, 230 deletions
diff --git a/Ryujinx.Graphics.Shader/Decoders/Decoder.cs b/Ryujinx.Graphics.Shader/Decoders/Decoder.cs index a15d7f9e..3f08bdd9 100644 --- a/Ryujinx.Graphics.Shader/Decoders/Decoder.cs +++ b/Ryujinx.Graphics.Shader/Decoders/Decoder.cs @@ -231,7 +231,7 @@ namespace Ryujinx.Graphics.Shader.Decoders long opCode = gpuAccessor.MemoryRead<long>(startAddress + opAddress); - (InstEmitter emitter, OpCodeTable.OpActivator opActivator) = OpCodeTable.GetEmitter(opCode); + (InstEmitter emitter, OpCodeTable.MakeOp makeOp) = OpCodeTable.GetEmitter(opCode); if (emitter == null) { @@ -242,12 +242,12 @@ namespace Ryujinx.Graphics.Shader.Decoders continue; } - if (opActivator == null) + if (makeOp == null) { - throw new ArgumentNullException(nameof(opActivator)); + throw new ArgumentNullException(nameof(makeOp)); } - OpCode op = (OpCode)opActivator(emitter, opAddress, opCode); + OpCode op = makeOp(emitter, opAddress, opCode); block.OpCodes.Add(op); } diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCode.cs b/Ryujinx.Graphics.Shader/Decoders/OpCode.cs index 94af49e0..27e10f89 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCode.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCode.cs @@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders // When inverted, the always true predicate == always false. public bool NeverExecute => Predicate.Index == RegisterConsts.PredicateTrueIndex && InvertPredicate; + public static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCode(emitter, address, opCode); + public OpCode(InstEmitter emitter, ulong address, long opCode) { Emitter = emitter; diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs index 15fbb9af..035aa730 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAlu.cs @@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool SetCondCode { get; protected set; } public bool Saturate { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAlu(emitter, address, opCode); + public OpCodeAlu(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs index 9c127989..04ef64df 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluCbuf(emitter, address, opCode); + public OpCodeAluCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs index a407fc6b..7faa0d80 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm(emitter, address, opCode); + public OpCodeAluImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeS20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs index 9aeb32bd..b475c8a9 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm2x10.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm2x10(emitter, address, opCode); + public OpCodeAluImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.Decode2xF10Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs index 5941e0b9..26b27a3d 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluImm32.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluImm32(emitter, address, opCode); + public OpCodeAluImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = opCode.Extract(20, 32); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs index 13b96a3a..fe61a51f 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluReg.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Register Rb { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluReg(emitter, address, opCode); + public OpCodeAluReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs index 6cf6bd2e..628fb472 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAluRegCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAluRegCbuf(emitter, address, opCode); + public OpCodeAluRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs index b572703e..1bf5d0cd 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAtom.cs @@ -16,6 +16,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public AtomicOp AtomicOp { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAtom(emitter, address, opCode); + public OpCodeAtom(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs index fd8e63fc..1457b602 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeAttribute.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int AttributeOffset { get; } public int Count { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeAttribute(emitter, address, opCode); + public OpCodeAttribute(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { AttributeOffset = opCode.Extract(20, 10); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs index 81e28aa1..7c82c683 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBarrier.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public BarrierMode Mode { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBarrier(emitter, address, opCode); + public OpCodeBarrier(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Mode = (BarrierMode)((opCode >> 32) & 0x9b); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs index c4fa9212..71cb9bca 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranch.cs @@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool PushTarget { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranch(emitter, address, opCode); + public OpCodeBranch(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Condition = (Condition)(opCode & 0x1f); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs index 3e694e61..b3911d6a 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchIndir.cs @@ -11,6 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranchIndir(emitter, address, opCode); + public OpCodeBranchIndir(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { PossibleTargets = new HashSet<Block>(); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs index 7ea66fe4..f6c3e4f4 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeBranchPop.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Dictionary<OpCodePush, int> Targets { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeBranchPop(emitter, address, opCode); + public OpCodeBranchPop(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Targets = new Dictionary<OpCodePush, int>(); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs index 99d4cdfd..f13bfc47 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeDArithImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public float Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeDArithImm(emitter, address, opCode); + public OpCodeDArithImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeD20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs index d50903eb..caad26a3 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeExit.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Condition Condition { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeExit(emitter, address, opCode); + public OpCodeExit(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Condition = (Condition)opCode.Extract(0, 5); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs index cfbf65c3..d262f157 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArith.cs @@ -11,6 +11,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool FlushToZero { get; } public bool AbsoluteA { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArith(emitter, address, opCode); + public OpCodeFArith(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { RoundingMode = (RoundingMode)opCode.Extract(39, 2); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs index 5486bb0b..1475f11b 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithCbuf(emitter, address, opCode); + public OpCodeFArithCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs index 1bb6f425..91a6561b 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public float Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithImm(emitter, address, opCode); + public OpCodeFArithImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeF20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs index aecc5143..09d0a13d 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithImm32.cs @@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public float Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithImm32(emitter, address, opCode); + public OpCodeFArithImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { int imm = opCode.Extract(20, 32); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs index 55cf4485..f4b64584 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithReg.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Register Rb { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithReg(emitter, address, opCode); + public OpCodeFArithReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs index 315c2c8b..c1b5cca6 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFArithRegCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFArithRegCbuf(emitter, address, opCode); + public OpCodeFArithRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs index cb5f155e..aa216db2 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeFsetImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public float Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeFsetImm(emitter, address, opCode); + public OpCodeFsetImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeF20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs index 32f3cd7a..9123cb97 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfma.cs @@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleA { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfma(emitter, address, opCode); + public OpCodeHfma(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs index 33768c7d..d73223ab 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaCbuf.cs @@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP32; public FPHalfSwizzle SwizzleC { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaCbuf(emitter, address, opCode); + public OpCodeHfmaCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs index 80a5a140..c847be0f 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm2x10.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP16; public FPHalfSwizzle SwizzleC { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaImm2x10(emitter, address, opCode); + public OpCodeHfmaImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.Decode2xF10Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs index 05eb9ffe..6d1ab265 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaImm32.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleB => FPHalfSwizzle.FP16; public FPHalfSwizzle SwizzleC => FPHalfSwizzle.FP16; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaImm32(emitter, address, opCode); + public OpCodeHfmaImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = opCode.Extract(20, 32); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs index 714c89de..ebb1fec9 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaReg.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleB { get; } public FPHalfSwizzle SwizzleC { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaReg(emitter, address, opCode); + public OpCodeHfmaReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs index c0001908..dc5d2fe9 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHfmaRegCbuf.cs @@ -14,6 +14,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public FPHalfSwizzle SwizzleB { get; } public FPHalfSwizzle SwizzleC => FPHalfSwizzle.FP32; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHfmaRegCbuf(emitter, address, opCode); + public OpCodeHfmaRegCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs index 03e1e44c..d5af5049 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeHsetImm2x10.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeHsetImm2x10(emitter, address, opCode); + public OpCodeHsetImm2x10(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.Decode2xF10Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs index 265d45a9..5b2f8063 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeImage.cs @@ -20,6 +20,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool UseComponents { get; } public bool IsBindless { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeImage(emitter, address, opCode); + public OpCodeImage(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs index b475b6a1..51138a1d 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeIpa.cs @@ -8,6 +8,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public InterpolationMode Mode { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeIpa(emitter, address, opCode); + public OpCodeIpa(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { AttributeOffset = opCode.Extract(28, 10); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs index 05bac28c..28d34d5a 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLdc.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public CbIndexMode IndexMode { get; } public IntegerSize Size { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLdc(emitter, address, opCode); + public OpCodeLdc(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs index c5f90345..45399de0 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLop.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public Register Predicate48 { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLop(emitter, address, opCode); + public OpCodeLop(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { InvertA = opCode.Extract(39); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs index f174733c..7a32382a 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopCbuf(emitter, address, opCode); + public OpCodeLopCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs index a2f091a2..b2443688 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopImm(emitter, address, opCode); + public OpCodeLopImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeS20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs index cb48f3a6..a751c2cd 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopImm32.cs @@ -9,6 +9,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool InvertA { get; } public bool InvertB { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopImm32(emitter, address, opCode); + public OpCodeLopImm32(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { LogicalOp = (LogicalOperation)opCode.Extract(53, 2); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs index 5f43db72..d14e4920 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeLopReg.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Register Rb { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeLopReg(emitter, address, opCode); + public OpCodeLopReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs index a0a9c8ca..65da3aed 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemory.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public IntegerSize Size { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeMemory(emitter, address, opCode); + public OpCodeMemory(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs index c31fe87b..c086b460 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeMemoryBarrier.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public BarrierLevel Level { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeMemoryBarrier(emitter, address, opCode); + public OpCodeMemoryBarrier(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Level = (BarrierLevel)opCode.Extract(8, 2); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs index df508442..9d88b863 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodePset.cs @@ -12,6 +12,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public LogicalOperation LogicalOpAB { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodePset(emitter, address, opCode); + public OpCodePset(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Predicate12 = new Register(opCode.Extract(12, 3), RegisterType.Predicate); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs index a7657bcf..4f00a069 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodePush.cs @@ -8,6 +8,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Dictionary<OpCodeBranchPop, Operand> PopOps { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodePush(emitter, address, opCode); + public OpCodePush(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { PopOps = new Dictionary<OpCodeBranchPop, Operand>(); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs index 2629d289..98bf9939 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeRed.cs @@ -15,6 +15,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Extended { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeRed(emitter, address, opCode); + public OpCodeRed(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs index b4ee10fb..94ed0bee 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSet.cs @@ -13,6 +13,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool FlushToZero { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSet(emitter, address, opCode); + public OpCodeSet(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Predicate0 = new Register(opCode.Extract(0, 3), RegisterType.Predicate); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs index 4f3dbd74..4e0eccf9 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetCbuf.cs @@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int Offset { get; } public int Slot { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetCbuf(emitter, address, opCode); + public OpCodeSetCbuf(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Offset = opCode.Extract(20, 14); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs index bc63b9f4..7c82c07c 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetImm.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public int Immediate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetImm(emitter, address, opCode); + public OpCodeSetImm(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Immediate = DecoderHelper.DecodeS20Immediate(opCode); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs index bbdee196..8ef0d7e4 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSetReg.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public Register Rb { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSetReg(emitter, address, opCode); + public OpCodeSetReg(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs index 43693cf4..f9f42433 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeShuffle.cs @@ -19,6 +19,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public Register Predicate48 { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeShuffle(emitter, address, opCode); + public OpCodeShuffle(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs index 1b5f5c7c..61168b59 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs @@ -1,12 +1,11 @@ using Ryujinx.Graphics.Shader.Instructions; using System; -using System.Reflection.Emit; namespace Ryujinx.Graphics.Shader.Decoders { static class OpCodeTable { - public delegate object OpActivator(InstEmitter emitter, ulong address, long opCode); + public delegate OpCode MakeOp(InstEmitter emitter, ulong address, long opCode); private const int EncodingBits = 14; @@ -14,35 +13,15 @@ namespace Ryujinx.Graphics.Shader.Decoders { public InstEmitter Emitter { get; } - public Type OpCodeType { get; } + public MakeOp MakeOp { get; } public int XBits { get; } - public OpActivator OpActivator { get; } - - public TableEntry(InstEmitter emitter, Type opCodeType, int xBits) - { - Emitter = emitter; - OpCodeType = opCodeType; - XBits = xBits; - OpActivator = CacheOpActivator(opCodeType); - } - - private static OpActivator CacheOpActivator(Type type) + public TableEntry(InstEmitter emitter, MakeOp makeOp, int xBits) { - Type[] argTypes = new Type[] { typeof(InstEmitter), typeof(ulong), typeof(long) }; - - DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes); - - ILGenerator generator = mthd.GetILGenerator(); - - generator.Emit(OpCodes.Ldarg_0); - generator.Emit(OpCodes.Ldarg_1); - generator.Emit(OpCodes.Ldarg_2); - generator.Emit(OpCodes.Newobj, type.GetConstructor(argTypes)); - generator.Emit(OpCodes.Ret); - - return (OpActivator)mthd.CreateDelegate(typeof(OpActivator)); + Emitter = emitter; + MakeOp = makeOp; + XBits = xBits; } } @@ -53,205 +32,205 @@ namespace Ryujinx.Graphics.Shader.Decoders _opCodes = new TableEntry[1 << EncodingBits]; #region Instructions - Set("1110111111011x", InstEmit.Ald, typeof(OpCodeAttribute)); - Set("1110111111110x", InstEmit.Ast, typeof(OpCodeAttribute)); - Set("11101100xxxxxx", InstEmit.Atoms, typeof(OpCodeAtom)); - Set("1111000010101x", InstEmit.Bar, typeof(OpCodeBarrier)); - Set("0100110000000x", InstEmit.Bfe, typeof(OpCodeAluCbuf)); - Set("0011100x00000x", InstEmit.Bfe, typeof(OpCodeAluImm)); - Set("0101110000000x", InstEmit.Bfe, typeof(OpCodeAluReg)); - Set("0100101111110x", InstEmit.Bfi, typeof(OpCodeAluCbuf)); - Set("0011011x11110x", InstEmit.Bfi, typeof(OpCodeAluImm)); - Set("0101001111110x", InstEmit.Bfi, typeof(OpCodeAluRegCbuf)); - Set("0101101111110x", InstEmit.Bfi, typeof(OpCodeAluReg)); - Set("111000100100xx", InstEmit.Bra, typeof(OpCodeBranch)); - Set("111000110100xx", InstEmit.Brk, typeof(OpCodeBranchPop)); - Set("111000100101xx", InstEmit.Brx, typeof(OpCodeBranchIndir)); - Set("0101000010100x", InstEmit.Csetp, typeof(OpCodePset)); - Set("0100110001110x", InstEmit.Dadd, typeof(OpCodeFArithCbuf)); - Set("0011100x01110x", InstEmit.Dadd, typeof(OpCodeDArithImm)); - Set("0101110001110x", InstEmit.Dadd, typeof(OpCodeFArithReg)); - Set("1111000011110x", InstEmit.Depbar, typeof(OpCode)); - Set("010010110111xx", InstEmit.Dfma, typeof(OpCodeFArithCbuf)); - Set("0011011x0111xx", InstEmit.Dfma, typeof(OpCodeDArithImm)); - Set("010100110111xx", InstEmit.Dfma, typeof(OpCodeFArithRegCbuf)); - Set("010110110111xx", InstEmit.Dfma, typeof(OpCodeFArithReg)); - Set("0100110010000x", InstEmit.Dmul, typeof(OpCodeFArithCbuf)); - Set("0011100x10000x", InstEmit.Dmul, typeof(OpCodeDArithImm)); - Set("0101110010000x", InstEmit.Dmul, typeof(OpCodeFArithReg)); - Set("111000110000xx", InstEmit.Exit, typeof(OpCodeExit)); - Set("0100110010101x", InstEmit.F2F, typeof(OpCodeFArithCbuf)); - Set("0011100x10101x", InstEmit.F2F, typeof(OpCodeFArithImm)); - Set("0101110010101x", InstEmit.F2F, typeof(OpCodeFArithReg)); - Set("0100110010110x", InstEmit.F2I, typeof(OpCodeFArithCbuf)); - Set("0011100x10110x", InstEmit.F2I, typeof(OpCodeFArithImm)); - Set("0101110010110x", InstEmit.F2I, typeof(OpCodeFArithReg)); - Set("0100110001011x", InstEmit.Fadd, typeof(OpCodeFArithCbuf)); - Set("0011100x01011x", InstEmit.Fadd, typeof(OpCodeFArithImm)); - Set("000010xxxxxxxx", InstEmit.Fadd, typeof(OpCodeFArithImm32)); - Set("0101110001011x", InstEmit.Fadd, typeof(OpCodeFArithReg)); - Set("010010111010xx", InstEmit.Fcmp, typeof(OpCodeFArithCbuf)); - Set("0011011x1010xx", InstEmit.Fcmp, typeof(OpCodeFArithImm)); - Set("010110111010xx", InstEmit.Fcmp, typeof(OpCodeFArithReg)); - Set("010100111010xx", InstEmit.Fcmp, typeof(OpCodeFArithRegCbuf)); - Set("010010011xxxxx", InstEmit.Ffma, typeof(OpCodeFArithCbuf)); - Set("0011001x1xxxxx", InstEmit.Ffma, typeof(OpCodeFArithImm)); - Set("000011xxxxxxxx", InstEmit.Ffma32i, typeof(OpCodeFArithImm32)); - Set("010100011xxxxx", InstEmit.Ffma, typeof(OpCodeFArithRegCbuf)); - Set("010110011xxxxx", InstEmit.Ffma, typeof(OpCodeFArithReg)); - Set("0100110000110x", InstEmit.Flo, typeof(OpCodeAluCbuf)); - Set("0011100x00110x", InstEmit.Flo, typeof(OpCodeAluImm)); - Set("0101110000110x", InstEmit.Flo, typeof(OpCodeAluReg)); - Set("0100110001100x", InstEmit.Fmnmx, typeof(OpCodeFArithCbuf)); - Set("0011100x01100x", InstEmit.Fmnmx, typeof(OpCodeFArithImm)); - Set("0101110001100x", InstEmit.Fmnmx, typeof(OpCodeFArithReg)); - Set("0100110001101x", InstEmit.Fmul, typeof(OpCodeFArithCbuf)); - Set("0011100x01101x", InstEmit.Fmul, typeof(OpCodeFArithImm)); - Set("00011110xxxxxx", InstEmit.Fmul, typeof(OpCodeFArithImm32)); - Set("0101110001101x", InstEmit.Fmul, typeof(OpCodeFArithReg)); - Set("0100100xxxxxxx", InstEmit.Fset, typeof(OpCodeSetCbuf)); - Set("0011000xxxxxxx", InstEmit.Fset, typeof(OpCodeFsetImm)); - Set("01011000xxxxxx", InstEmit.Fset, typeof(OpCodeSetReg)); - Set("010010111011xx", InstEmit.Fsetp, typeof(OpCodeSetCbuf)); - Set("0011011x1011xx", InstEmit.Fsetp, typeof(OpCodeFsetImm)); - Set("010110111011xx", InstEmit.Fsetp, typeof(OpCodeSetReg)); - Set("0101000011111x", InstEmit.Fswzadd, typeof(OpCodeAluReg)); - Set("0111101x1xxxxx", InstEmit.Hadd2, typeof(OpCodeAluCbuf)); - Set("0111101x0xxxxx", InstEmit.Hadd2, typeof(OpCodeAluImm2x10)); - Set("0010110xxxxxxx", InstEmit.Hadd2, typeof(OpCodeAluImm32)); - Set("0101110100010x", InstEmit.Hadd2, typeof(OpCodeAluReg)); - Set("01110xxx1xxxxx", InstEmit.Hfma2, typeof(OpCodeHfmaCbuf)); - Set("01110xxx0xxxxx", InstEmit.Hfma2, typeof(OpCodeHfmaImm2x10)); - Set("0010100xxxxxxx", InstEmit.Hfma2, typeof(OpCodeHfmaImm32)); - Set("0101110100000x", InstEmit.Hfma2, typeof(OpCodeHfmaReg)); - Set("01100xxx1xxxxx", InstEmit.Hfma2, typeof(OpCodeHfmaRegCbuf)); - Set("0111100x1xxxxx", InstEmit.Hmul2, typeof(OpCodeAluCbuf)); - Set("0111100x0xxxxx", InstEmit.Hmul2, typeof(OpCodeAluImm2x10)); - Set("0010101xxxxxxx", InstEmit.Hmul2, typeof(OpCodeAluImm32)); - Set("0101110100001x", InstEmit.Hmul2, typeof(OpCodeAluReg)); - Set("0111110x1xxxxx", InstEmit.Hset2, typeof(OpCodeSetCbuf)); - Set("0111110x0xxxxx", InstEmit.Hset2, typeof(OpCodeHsetImm2x10)); - Set("0101110100011x", InstEmit.Hset2, typeof(OpCodeSetReg)); - Set("0111111x1xxxxx", InstEmit.Hsetp2, typeof(OpCodeSetCbuf)); - Set("0111111x0xxxxx", InstEmit.Hsetp2, typeof(OpCodeHsetImm2x10)); - Set("0101110100100x", InstEmit.Hsetp2, typeof(OpCodeSetReg)); - Set("0100110010111x", InstEmit.I2F, typeof(OpCodeAluCbuf)); - Set("0011100x10111x", InstEmit.I2F, typeof(OpCodeAluImm)); - Set("0101110010111x", InstEmit.I2F, typeof(OpCodeAluReg)); - Set("0100110011100x", InstEmit.I2I, typeof(OpCodeAluCbuf)); - Set("0011100x11100x", InstEmit.I2I, typeof(OpCodeAluImm)); - Set("0101110011100x", InstEmit.I2I, typeof(OpCodeAluReg)); - Set("0100110000010x", InstEmit.Iadd, typeof(OpCodeAluCbuf)); - Set("0011100x00010x", InstEmit.Iadd, typeof(OpCodeAluImm)); - Set("0001110x0xxxxx", InstEmit.Iadd, typeof(OpCodeAluImm32)); - Set("0101110000010x", InstEmit.Iadd, typeof(OpCodeAluReg)); - Set("010011001100xx", InstEmit.Iadd3, typeof(OpCodeAluCbuf)); - Set("0011100x1100xx", InstEmit.Iadd3, typeof(OpCodeAluImm)); - Set("010111001100xx", InstEmit.Iadd3, typeof(OpCodeAluReg)); - Set("010010110100xx", InstEmit.Icmp, typeof(OpCodeAluCbuf)); - Set("0011011x0100xx", InstEmit.Icmp, typeof(OpCodeAluImm)); - Set("010110110100xx", InstEmit.Icmp, typeof(OpCodeAluReg)); - Set("010100110100xx", InstEmit.Icmp, typeof(OpCodeAluRegCbuf)); - Set("010010100xxxxx", InstEmit.Imad, typeof(OpCodeAluCbuf)); - Set("0011010x0xxxxx", InstEmit.Imad, typeof(OpCodeAluImm)); - Set("010110100xxxxx", InstEmit.Imad, typeof(OpCodeAluReg)); - Set("010100100xxxxx", InstEmit.Imad, typeof(OpCodeAluRegCbuf)); - Set("0100110000100x", InstEmit.Imnmx, typeof(OpCodeAluCbuf)); - Set("0011100x00100x", InstEmit.Imnmx, typeof(OpCodeAluImm)); - Set("0101110000100x", InstEmit.Imnmx, typeof(OpCodeAluReg)); - Set("11100000xxxxxx", InstEmit.Ipa, typeof(OpCodeIpa)); - Set("1110111111010x", InstEmit.Isberd, typeof(OpCodeAlu)); - Set("0100110000011x", InstEmit.Iscadd, typeof(OpCodeAluCbuf)); - Set("0011100x00011x", InstEmit.Iscadd, typeof(OpCodeAluImm)); - Set("000101xxxxxxxx", InstEmit.Iscadd, typeof(OpCodeAluImm32)); - Set("0101110000011x", InstEmit.Iscadd, typeof(OpCodeAluReg)); - Set("010010110101xx", InstEmit.Iset, typeof(OpCodeSetCbuf)); - Set("0011011x0101xx", InstEmit.Iset, typeof(OpCodeSetImm)); - Set("010110110101xx", InstEmit.Iset, typeof(OpCodeSetReg)); - Set("010010110110xx", InstEmit.Isetp, typeof(OpCodeSetCbuf)); - Set("0011011x0110xx", InstEmit.Isetp, typeof(OpCodeSetImm)); - Set("010110110110xx", InstEmit.Isetp, typeof(OpCodeSetReg)); - Set("111000110011xx", InstEmit.Kil, typeof(OpCodeExit)); - Set("1110111101000x", InstEmit.Ld, typeof(OpCodeMemory)); - Set("1110111110010x", InstEmit.Ldc, typeof(OpCodeLdc)); - Set("1110111011010x", InstEmit.Ldg, typeof(OpCodeMemory)); - Set("1110111101001x", InstEmit.Lds, typeof(OpCodeMemory)); - Set("010010111101xx", InstEmit.Lea, typeof(OpCodeAluCbuf)); - Set("0011011x11010x", InstEmit.Lea, typeof(OpCodeAluImm)); - Set("0101101111010x", InstEmit.Lea, typeof(OpCodeAluReg)); - Set("000110xxxxxxxx", InstEmit.Lea_Hi, typeof(OpCodeAluCbuf)); - Set("0101101111011x", InstEmit.Lea_Hi, typeof(OpCodeAluReg)); - Set("0100110001000x", InstEmit.Lop, typeof(OpCodeLopCbuf)); - Set("0011100001000x", InstEmit.Lop, typeof(OpCodeLopImm)); - Set("000001xxxxxxxx", InstEmit.Lop, typeof(OpCodeLopImm32)); - Set("0101110001000x", InstEmit.Lop, typeof(OpCodeLopReg)); - Set("0000001xxxxxxx", InstEmit.Lop3, typeof(OpCodeLopCbuf)); - Set("001111xxxxxxxx", InstEmit.Lop3, typeof(OpCodeLopImm)); - Set("0101101111100x", InstEmit.Lop3, typeof(OpCodeLopReg)); - Set("1110111110011x", InstEmit.Membar, typeof(OpCodeMemoryBarrier)); - Set("0100110010011x", InstEmit.Mov, typeof(OpCodeAluCbuf)); - Set("0011100x10011x", InstEmit.Mov, typeof(OpCodeAluImm)); - Set("000000010000xx", InstEmit.Mov, typeof(OpCodeAluImm32)); - Set("0101110010011x", InstEmit.Mov, typeof(OpCodeAluReg)); - Set("0101000010000x", InstEmit.Mufu, typeof(OpCodeFArith)); - Set("0101000010110x", InstEmit.Nop, typeof(OpCode)); - Set("1111101111100x", InstEmit.Out, typeof(OpCode)); - Set("111000101010xx", InstEmit.Pbk, typeof(OpCodePush)); - Set("0100110000001x", InstEmit.Popc, typeof(OpCodeAluCbuf)); - Set("0011100x00001x", InstEmit.Popc, typeof(OpCodeAluImm)); - Set("0101110000001x", InstEmit.Popc, typeof(OpCodeAluReg)); - Set("0101000010001x", InstEmit.Pset, typeof(OpCodePset)); - Set("0101000010010x", InstEmit.Psetp, typeof(OpCodePset)); - Set("0100110011110x", InstEmit.R2p, typeof(OpCodeAluCbuf)); - Set("0011100x11110x", InstEmit.R2p, typeof(OpCodeAluImm)); - Set("0101110011110x", InstEmit.R2p, typeof(OpCodeAluReg)); - Set("1110101111111x", InstEmit.Red, typeof(OpCodeRed)); - Set("0100110010010x", InstEmit.Rro, typeof(OpCodeFArithCbuf)); - Set("0011100x10010x", InstEmit.Rro, typeof(OpCodeFArithImm)); - Set("0101110010010x", InstEmit.Rro, typeof(OpCodeFArithReg)); - Set("1111000011001x", InstEmit.S2r, typeof(OpCodeAlu)); - Set("0100110010100x", InstEmit.Sel, typeof(OpCodeAluCbuf)); - Set("0011100x10100x", InstEmit.Sel, typeof(OpCodeAluImm)); - Set("0101110010100x", InstEmit.Sel, typeof(OpCodeAluReg)); - Set("1110111100010x", InstEmit.Shfl, typeof(OpCodeShuffle)); - Set("0100110001001x", InstEmit.Shl, typeof(OpCodeAluCbuf)); - Set("0011100x01001x", InstEmit.Shl, typeof(OpCodeAluImm)); - Set("0101110001001x", InstEmit.Shl, typeof(OpCodeAluReg)); - Set("0100110000101x", InstEmit.Shr, typeof(OpCodeAluCbuf)); - Set("0011100x00101x", InstEmit.Shr, typeof(OpCodeAluImm)); - Set("0101110000101x", InstEmit.Shr, typeof(OpCodeAluReg)); - Set("111000101001xx", InstEmit.Ssy, typeof(OpCodePush)); - Set("1110111101010x", InstEmit.St, typeof(OpCodeMemory)); - Set("1110111011011x", InstEmit.Stg, typeof(OpCodeMemory)); - Set("1110111101011x", InstEmit.Sts, typeof(OpCodeMemory)); - Set("11101011000xxx", InstEmit.Suld, typeof(OpCodeImage)); - Set("11101011001xxx", InstEmit.Sust, typeof(OpCodeImage)); - Set("1111000011111x", InstEmit.Sync, typeof(OpCodeBranchPop)); - Set("110000xxxx111x", InstEmit.Tex, typeof(OpCodeTex)); - Set("1101111010111x", InstEmit.TexB, typeof(OpCodeTexB)); - Set("1101x00xxxxxxx", InstEmit.Texs, typeof(OpCodeTexs)); - Set("1101x01xxxxxxx", InstEmit.Texs, typeof(OpCodeTlds)); - Set("11011111x0xxxx", InstEmit.Texs, typeof(OpCodeTld4s)); - Set("11011100xx111x", InstEmit.Tld, typeof(OpCodeTld)); - Set("11011101xx111x", InstEmit.TldB, typeof(OpCodeTld)); - Set("110010xxxx111x", InstEmit.Tld4, typeof(OpCodeTld4)); - Set("1101111011111x", InstEmit.Tld4, typeof(OpCodeTld4B)); - Set("11011111011000", InstEmit.TmmlB, typeof(OpCodeTexture)); - Set("11011111010110", InstEmit.Tmml, typeof(OpCodeTexture)); - Set("110111100x1110", InstEmit.Txd, typeof(OpCodeTxd)); - Set("1101111101001x", InstEmit.Txq, typeof(OpCodeTex)); - Set("1101111101010x", InstEmit.TxqB, typeof(OpCodeTex)); - Set("01011111xxxxxx", InstEmit.Vmad, typeof(OpCodeVideo)); - Set("0011101xxxxxxx", InstEmit.Vmnmx, typeof(OpCodeVideo)); - Set("0101000011011x", InstEmit.Vote, typeof(OpCodeVote)); - Set("0100111xxxxxxx", InstEmit.Xmad, typeof(OpCodeAluCbuf)); - Set("0011011x00xxxx", InstEmit.Xmad, typeof(OpCodeAluImm)); - Set("010100010xxxxx", InstEmit.Xmad, typeof(OpCodeAluRegCbuf)); - Set("0101101100xxxx", InstEmit.Xmad, typeof(OpCodeAluReg)); + Set("1110111111011x", InstEmit.Ald, OpCodeAttribute.Create); + Set("1110111111110x", InstEmit.Ast, OpCodeAttribute.Create); + Set("11101100xxxxxx", InstEmit.Atoms, OpCodeAtom.Create); + Set("1111000010101x", InstEmit.Bar, OpCodeBarrier.Create); + Set("0100110000000x", InstEmit.Bfe, OpCodeAluCbuf.Create); + Set("0011100x00000x", InstEmit.Bfe, OpCodeAluImm.Create); + Set("0101110000000x", InstEmit.Bfe, OpCodeAluReg.Create); + Set("0100101111110x", InstEmit.Bfi, OpCodeAluCbuf.Create); + Set("0011011x11110x", InstEmit.Bfi, OpCodeAluImm.Create); + Set("0101001111110x", InstEmit.Bfi, OpCodeAluRegCbuf.Create); + Set("0101101111110x", InstEmit.Bfi, OpCodeAluReg.Create); + Set("111000100100xx", InstEmit.Bra, OpCodeBranch.Create); + Set("111000110100xx", InstEmit.Brk, OpCodeBranchPop.Create); + Set("111000100101xx", InstEmit.Brx, OpCodeBranchIndir.Create); + Set("0101000010100x", InstEmit.Csetp, OpCodePset.Create); + Set("0100110001110x", InstEmit.Dadd, OpCodeFArithCbuf.Create); + Set("0011100x01110x", InstEmit.Dadd, OpCodeDArithImm.Create); + Set("0101110001110x", InstEmit.Dadd, OpCodeFArithReg.Create); + Set("1111000011110x", InstEmit.Depbar, OpCode.Create); + Set("010010110111xx", InstEmit.Dfma, OpCodeFArithCbuf.Create); + Set("0011011x0111xx", InstEmit.Dfma, OpCodeDArithImm.Create); + Set("010100110111xx", InstEmit.Dfma, OpCodeFArithRegCbuf.Create); + Set("010110110111xx", InstEmit.Dfma, OpCodeFArithReg.Create); + Set("0100110010000x", InstEmit.Dmul, OpCodeFArithCbuf.Create); + Set("0011100x10000x", InstEmit.Dmul, OpCodeDArithImm.Create); + Set("0101110010000x", InstEmit.Dmul, OpCodeFArithReg.Create); + Set("111000110000xx", InstEmit.Exit, OpCodeExit.Create); + Set("0100110010101x", InstEmit.F2F, OpCodeFArithCbuf.Create); + Set("0011100x10101x", InstEmit.F2F, OpCodeFArithImm.Create); + Set("0101110010101x", InstEmit.F2F, OpCodeFArithReg.Create); + Set("0100110010110x", InstEmit.F2I, OpCodeFArithCbuf.Create); + Set("0011100x10110x", InstEmit.F2I, OpCodeFArithImm.Create); + Set("0101110010110x", InstEmit.F2I, OpCodeFArithReg.Create); + Set("0100110001011x", InstEmit.Fadd, OpCodeFArithCbuf.Create); + Set("0011100x01011x", InstEmit.Fadd, OpCodeFArithImm.Create); + Set("000010xxxxxxxx", InstEmit.Fadd, OpCodeFArithImm32.Create); + Set("0101110001011x", InstEmit.Fadd, OpCodeFArithReg.Create); + Set("010010111010xx", InstEmit.Fcmp, OpCodeFArithCbuf.Create); + Set("0011011x1010xx", InstEmit.Fcmp, OpCodeFArithImm.Create); + Set("010110111010xx", InstEmit.Fcmp, OpCodeFArithReg.Create); + Set("010100111010xx", InstEmit.Fcmp, OpCodeFArithRegCbuf.Create); + Set("010010011xxxxx", InstEmit.Ffma, OpCodeFArithCbuf.Create); + Set("0011001x1xxxxx", InstEmit.Ffma, OpCodeFArithImm.Create); + Set("000011xxxxxxxx", InstEmit.Ffma32i, OpCodeFArithImm32.Create); + Set("010100011xxxxx", InstEmit.Ffma, OpCodeFArithRegCbuf.Create); + Set("010110011xxxxx", InstEmit.Ffma, OpCodeFArithReg.Create); + Set("0100110000110x", InstEmit.Flo, OpCodeAluCbuf.Create); + Set("0011100x00110x", InstEmit.Flo, OpCodeAluImm.Create); + Set("0101110000110x", InstEmit.Flo, OpCodeAluReg.Create); + Set("0100110001100x", InstEmit.Fmnmx, OpCodeFArithCbuf.Create); + Set("0011100x01100x", InstEmit.Fmnmx, OpCodeFArithImm.Create); + Set("0101110001100x", InstEmit.Fmnmx, OpCodeFArithReg.Create); + Set("0100110001101x", InstEmit.Fmul, OpCodeFArithCbuf.Create); + Set("0011100x01101x", InstEmit.Fmul, OpCodeFArithImm.Create); + Set("00011110xxxxxx", InstEmit.Fmul, OpCodeFArithImm32.Create); + Set("0101110001101x", InstEmit.Fmul, OpCodeFArithReg.Create); + Set("0100100xxxxxxx", InstEmit.Fset, OpCodeSetCbuf.Create); + Set("0011000xxxxxxx", InstEmit.Fset, OpCodeFsetImm.Create); + Set("01011000xxxxxx", InstEmit.Fset, OpCodeSetReg.Create); + Set("010010111011xx", InstEmit.Fsetp, OpCodeSetCbuf.Create); + Set("0011011x1011xx", InstEmit.Fsetp, OpCodeFsetImm.Create); + Set("010110111011xx", InstEmit.Fsetp, OpCodeSetReg.Create); + Set("0101000011111x", InstEmit.Fswzadd, OpCodeAluReg.Create); + Set("0111101x1xxxxx", InstEmit.Hadd2, OpCodeAluCbuf.Create); + Set("0111101x0xxxxx", InstEmit.Hadd2, OpCodeAluImm2x10.Create); + Set("0010110xxxxxxx", InstEmit.Hadd2, OpCodeAluImm32.Create); + Set("0101110100010x", InstEmit.Hadd2, OpCodeAluReg.Create); + Set("01110xxx1xxxxx", InstEmit.Hfma2, OpCodeHfmaCbuf.Create); + Set("01110xxx0xxxxx", InstEmit.Hfma2, OpCodeHfmaImm2x10.Create); + Set("0010100xxxxxxx", InstEmit.Hfma2, OpCodeHfmaImm32.Create); + Set("0101110100000x", InstEmit.Hfma2, OpCodeHfmaReg.Create); + Set("01100xxx1xxxxx", InstEmit.Hfma2, OpCodeHfmaRegCbuf.Create); + Set("0111100x1xxxxx", InstEmit.Hmul2, OpCodeAluCbuf.Create); + Set("0111100x0xxxxx", InstEmit.Hmul2, OpCodeAluImm2x10.Create); + Set("0010101xxxxxxx", InstEmit.Hmul2, OpCodeAluImm32.Create); + Set("0101110100001x", InstEmit.Hmul2, OpCodeAluReg.Create); + Set("0111110x1xxxxx", InstEmit.Hset2, OpCodeSetCbuf.Create); + Set("0111110x0xxxxx", InstEmit.Hset2, OpCodeHsetImm2x10.Create); + Set("0101110100011x", InstEmit.Hset2, OpCodeSetReg.Create); + Set("0111111x1xxxxx", InstEmit.Hsetp2, OpCodeSetCbuf.Create); + Set("0111111x0xxxxx", InstEmit.Hsetp2, OpCodeHsetImm2x10.Create); + Set("0101110100100x", InstEmit.Hsetp2, OpCodeSetReg.Create); + Set("0100110010111x", InstEmit.I2F, OpCodeAluCbuf.Create); + Set("0011100x10111x", InstEmit.I2F, OpCodeAluImm.Create); + Set("0101110010111x", InstEmit.I2F, OpCodeAluReg.Create); + Set("0100110011100x", InstEmit.I2I, OpCodeAluCbuf.Create); + Set("0011100x11100x", InstEmit.I2I, OpCodeAluImm.Create); + Set("0101110011100x", InstEmit.I2I, OpCodeAluReg.Create); + Set("0100110000010x", InstEmit.Iadd, OpCodeAluCbuf.Create); + Set("0011100x00010x", InstEmit.Iadd, OpCodeAluImm.Create); + Set("0001110x0xxxxx", InstEmit.Iadd, OpCodeAluImm32.Create); + Set("0101110000010x", InstEmit.Iadd, OpCodeAluReg.Create); + Set("010011001100xx", InstEmit.Iadd3, OpCodeAluCbuf.Create); + Set("0011100x1100xx", InstEmit.Iadd3, OpCodeAluImm.Create); + Set("010111001100xx", InstEmit.Iadd3, OpCodeAluReg.Create); + Set("010010110100xx", InstEmit.Icmp, OpCodeAluCbuf.Create); + Set("0011011x0100xx", InstEmit.Icmp, OpCodeAluImm.Create); + Set("010110110100xx", InstEmit.Icmp, OpCodeAluReg.Create); + Set("010100110100xx", InstEmit.Icmp, OpCodeAluRegCbuf.Create); + Set("010010100xxxxx", InstEmit.Imad, OpCodeAluCbuf.Create); + Set("0011010x0xxxxx", InstEmit.Imad, OpCodeAluImm.Create); + Set("010110100xxxxx", InstEmit.Imad, OpCodeAluReg.Create); + Set("010100100xxxxx", InstEmit.Imad, OpCodeAluRegCbuf.Create); + Set("0100110000100x", InstEmit.Imnmx, OpCodeAluCbuf.Create); + Set("0011100x00100x", InstEmit.Imnmx, OpCodeAluImm.Create); + Set("0101110000100x", InstEmit.Imnmx, OpCodeAluReg.Create); + Set("11100000xxxxxx", InstEmit.Ipa, OpCodeIpa.Create); + Set("1110111111010x", InstEmit.Isberd, OpCodeAlu.Create); + Set("0100110000011x", InstEmit.Iscadd, OpCodeAluCbuf.Create); + Set("0011100x00011x", InstEmit.Iscadd, OpCodeAluImm.Create); + Set("000101xxxxxxxx", InstEmit.Iscadd, OpCodeAluImm32.Create); + Set("0101110000011x", InstEmit.Iscadd, OpCodeAluReg.Create); + Set("010010110101xx", InstEmit.Iset, OpCodeSetCbuf.Create); + Set("0011011x0101xx", InstEmit.Iset, OpCodeSetImm.Create); + Set("010110110101xx", InstEmit.Iset, OpCodeSetReg.Create); + Set("010010110110xx", InstEmit.Isetp, OpCodeSetCbuf.Create); + Set("0011011x0110xx", InstEmit.Isetp, OpCodeSetImm.Create); + Set("010110110110xx", InstEmit.Isetp, OpCodeSetReg.Create); + Set("111000110011xx", InstEmit.Kil, OpCodeExit.Create); + Set("1110111101000x", InstEmit.Ld, OpCodeMemory.Create); + Set("1110111110010x", InstEmit.Ldc, OpCodeLdc.Create); + Set("1110111011010x", InstEmit.Ldg, OpCodeMemory.Create); + Set("1110111101001x", InstEmit.Lds, OpCodeMemory.Create); + Set("010010111101xx", InstEmit.Lea, OpCodeAluCbuf.Create); + Set("0011011x11010x", InstEmit.Lea, OpCodeAluImm.Create); + Set("0101101111010x", InstEmit.Lea, OpCodeAluReg.Create); + Set("000110xxxxxxxx", InstEmit.Lea_Hi, OpCodeAluCbuf.Create); + Set("0101101111011x", InstEmit.Lea_Hi, OpCodeAluReg.Create); + Set("0100110001000x", InstEmit.Lop, OpCodeLopCbuf.Create); + Set("0011100001000x", InstEmit.Lop, OpCodeLopImm.Create); + Set("000001xxxxxxxx", InstEmit.Lop, OpCodeLopImm32.Create); + Set("0101110001000x", InstEmit.Lop, OpCodeLopReg.Create); + Set("0000001xxxxxxx", InstEmit.Lop3, OpCodeLopCbuf.Create); + Set("001111xxxxxxxx", InstEmit.Lop3, OpCodeLopImm.Create); + Set("0101101111100x", InstEmit.Lop3, OpCodeLopReg.Create); + Set("1110111110011x", InstEmit.Membar, OpCodeMemoryBarrier.Create); + Set("0100110010011x", InstEmit.Mov, OpCodeAluCbuf.Create); + Set("0011100x10011x", InstEmit.Mov, OpCodeAluImm.Create); + Set("000000010000xx", InstEmit.Mov, OpCodeAluImm32.Create); + Set("0101110010011x", InstEmit.Mov, OpCodeAluReg.Create); + Set("0101000010000x", InstEmit.Mufu, OpCodeFArith.Create); + Set("0101000010110x", InstEmit.Nop, OpCode.Create); + Set("1111101111100x", InstEmit.Out, OpCode.Create); + Set("111000101010xx", InstEmit.Pbk, OpCodePush.Create); + Set("0100110000001x", InstEmit.Popc, OpCodeAluCbuf.Create); + Set("0011100x00001x", InstEmit.Popc, OpCodeAluImm.Create); + Set("0101110000001x", InstEmit.Popc, OpCodeAluReg.Create); + Set("0101000010001x", InstEmit.Pset, OpCodePset.Create); + Set("0101000010010x", InstEmit.Psetp, OpCodePset.Create); + Set("0100110011110x", InstEmit.R2p, OpCodeAluCbuf.Create); + Set("0011100x11110x", InstEmit.R2p, OpCodeAluImm.Create); + Set("0101110011110x", InstEmit.R2p, OpCodeAluReg.Create); + Set("1110101111111x", InstEmit.Red, OpCodeRed.Create); + Set("0100110010010x", InstEmit.Rro, OpCodeFArithCbuf.Create); + Set("0011100x10010x", InstEmit.Rro, OpCodeFArithImm.Create); + Set("0101110010010x", InstEmit.Rro, OpCodeFArithReg.Create); + Set("1111000011001x", InstEmit.S2r, OpCodeAlu.Create); + Set("0100110010100x", InstEmit.Sel, OpCodeAluCbuf.Create); + Set("0011100x10100x", InstEmit.Sel, OpCodeAluImm.Create); + Set("0101110010100x", InstEmit.Sel, OpCodeAluReg.Create); + Set("1110111100010x", InstEmit.Shfl, OpCodeShuffle.Create); + Set("0100110001001x", InstEmit.Shl, OpCodeAluCbuf.Create); + Set("0011100x01001x", InstEmit.Shl, OpCodeAluImm.Create); + Set("0101110001001x", InstEmit.Shl, OpCodeAluReg.Create); + Set("0100110000101x", InstEmit.Shr, OpCodeAluCbuf.Create); + Set("0011100x00101x", InstEmit.Shr, OpCodeAluImm.Create); + Set("0101110000101x", InstEmit.Shr, OpCodeAluReg.Create); + Set("111000101001xx", InstEmit.Ssy, OpCodePush.Create); + Set("1110111101010x", InstEmit.St, OpCodeMemory.Create); + Set("1110111011011x", InstEmit.Stg, OpCodeMemory.Create); + Set("1110111101011x", InstEmit.Sts, OpCodeMemory.Create); + Set("11101011000xxx", InstEmit.Suld, OpCodeImage.Create); + Set("11101011001xxx", InstEmit.Sust, OpCodeImage.Create); + Set("1111000011111x", InstEmit.Sync, OpCodeBranchPop.Create); + Set("110000xxxx111x", InstEmit.Tex, OpCodeTex.Create); + Set("1101111010111x", InstEmit.TexB, OpCodeTexB.Create); + Set("1101x00xxxxxxx", InstEmit.Texs, OpCodeTexs.Create); + Set("1101x01xxxxxxx", InstEmit.Texs, OpCodeTlds.Create); + Set("11011111x0xxxx", InstEmit.Texs, OpCodeTld4s.Create); + Set("11011100xx111x", InstEmit.Tld, OpCodeTld.Create); + Set("11011101xx111x", InstEmit.TldB, OpCodeTld.Create); + Set("110010xxxx111x", InstEmit.Tld4, OpCodeTld4.Create); + Set("1101111011111x", InstEmit.Tld4, OpCodeTld4B.Create); + Set("11011111011000", InstEmit.TmmlB, OpCodeTexture.Create); + Set("11011111010110", InstEmit.Tmml, OpCodeTexture.Create); + Set("110111100x1110", InstEmit.Txd, OpCodeTxd.Create); + Set("1101111101001x", InstEmit.Txq, OpCodeTex.Create); + Set("1101111101010x", InstEmit.TxqB, OpCodeTex.Create); + Set("01011111xxxxxx", InstEmit.Vmad, OpCodeVideo.Create); + Set("0011101xxxxxxx", InstEmit.Vmnmx, OpCodeVideo.Create); + Set("0101000011011x", InstEmit.Vote, OpCodeVote.Create); + Set("0100111xxxxxxx", InstEmit.Xmad, OpCodeAluCbuf.Create); + Set("0011011x00xxxx", InstEmit.Xmad, OpCodeAluImm.Create); + Set("010100010xxxxx", InstEmit.Xmad, OpCodeAluRegCbuf.Create); + Set("0101101100xxxx", InstEmit.Xmad, OpCodeAluReg.Create); #endregion } - private static void Set(string encoding, InstEmitter emitter, Type opCodeType) + private static void Set(string encoding, InstEmitter emitter, MakeOp makeOp) { if (encoding.Length != EncodingBits) { @@ -283,7 +262,7 @@ namespace Ryujinx.Graphics.Shader.Decoders xMask = ~xMask; - TableEntry entry = new TableEntry(emitter, opCodeType, xBits); + TableEntry entry = new TableEntry(emitter, makeOp, xBits); for (int index = 0; index < (1 << xBits); index++) { @@ -301,13 +280,13 @@ namespace Ryujinx.Graphics.Shader.Decoders } } - public static (InstEmitter emitter, OpActivator opActivator) GetEmitter(long opCode) + public static (InstEmitter Emitter, MakeOp MakeOp) GetEmitter(long opCode) { TableEntry entry = _opCodes[(ulong)opCode >> (64 - EncodingBits)]; if (entry != null) { - return (entry.Emitter, entry.OpActivator); + return (entry.Emitter, entry.MakeOp); } return (null, null); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs index da8756b9..c0e4da02 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTex.cs @@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { class OpCodeTex : OpCodeTexture { + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTex(emitter, address, opCode); + public OpCodeTex(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasDepthCompare = opCode.Extract(50); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs index b18bf3be..33434ae1 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexB.cs @@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { class OpCodeTexB : OpCodeTex { + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexB(emitter, address, opCode); + public OpCodeTexB(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { switch (opCode.Extract(37, 3)) diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs index fb90ccf6..ea3057c8 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexs.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public TextureTarget Target => (TextureTarget)RawType; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexs(emitter, address, opCode); + public OpCodeTexs(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { } } }
\ No newline at end of file diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs index 76e95118..f19f7dad 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTexture.cs @@ -22,6 +22,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool HasDepthCompare { get; protected set; } public bool IsMultisample { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTexture(emitter, address, opCode); + public OpCodeTexture(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs index 543f8d13..3ccd185c 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTextureScalar.cs @@ -41,6 +41,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool IsFp16 { get; protected set; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTextureScalar(emitter, address, opCode); + public OpCodeTextureScalar(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd0 = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs index 61bd900b..199cf234 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld.cs @@ -4,6 +4,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { class OpCodeTld : OpCodeTexture { + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld(emitter, address, opCode); + public OpCodeTld(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasOffset = opCode.Extract(35); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs index 0ffafbe1..db6572ad 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4.cs @@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Bindless => false; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4(emitter, address, opCode); + public OpCodeTld4(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasDepthCompare = opCode.Extract(50); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs index dc274d14..a3988d00 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4B.cs @@ -10,6 +10,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool Bindless => true; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4B(emitter, address, opCode); + public OpCodeTld4B(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasDepthCompare = opCode.Extract(50); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs index fd3240a0..442d36da 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTld4s.cs @@ -9,6 +9,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public int GatherCompIndex { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTld4s(emitter, address, opCode); + public OpCodeTld4s(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasDepthCompare = opCode.Extract(50); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs index 1e4e943f..97b328c4 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTlds.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public TexelLoadTarget Target => (TexelLoadTarget)RawType; + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTlds(emitter, address, opCode); + public OpCodeTlds(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { } } }
\ No newline at end of file diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs index 25df1f81..63185a1b 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTxd.cs @@ -6,6 +6,8 @@ namespace Ryujinx.Graphics.Shader.Decoders { public bool IsBindless { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeTxd(emitter, address, opCode); + public OpCodeTxd(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { HasOffset = opCode.Extract(35); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs index c2bdc22f..786b81dc 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeVideo.cs @@ -26,6 +26,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool DstSigned { get; } public bool Saturate { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeVideo(emitter, address, opCode); + public OpCodeVideo(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs index 374767bd..4fc988bc 100644 --- a/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs +++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeVote.cs @@ -12,6 +12,8 @@ namespace Ryujinx.Graphics.Shader.Decoders public bool InvertP { get; } + public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeVote(emitter, address, opCode); + public OpCodeVote(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode) { Rd = new Register(opCode.Extract(0, 8), RegisterType.Gpr); |