Implement Shader Instructions SUATOM and SURED (#2090)

* Initial Implementation

* Further improvements (no support for float/64-bit types)

* Merge atomic and reduce instructions, add missing format switch

* Fix rebase issues.

* Not used.

* Whoops. Fixed.

* Partial implementation of inc/dec, cleanup and TODOs

* Remove testing path

* Address Feedback

4 files changed, 98 insertions, 1 deletions

diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSuatom.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSuatom.cs
new file mode 100644
index 00000000..7c807b36
--- /dev/null
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSuatom.cs
@@ -0,0 +1,46 @@
+using Ryujinx.Graphics.Shader.Instructions;
+
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    class OpCodeSuatom : OpCodeTextureBase
+    {
+        public Register Rd { get; }
+        public Register Ra { get; }
+        public Register Rb { get; }
+        public Register Rc { get; }
+
+        public ReductionType Type { get; }
+        public AtomicOp AtomicOp { get; }
+        public ImageDimensions Dimensions { get; }
+        public ClampMode ClampMode { get; }
+
+        public bool ByteAddress { get; }
+        public bool UseType { get; }
+        public bool IsBindless { get; }
+
+        public bool CompareAndSwap { get; }
+
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSuatom(emitter, address, opCode);
+
+        public OpCodeSuatom(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
+        {
+            Rd = new Register(opCode.Extract(0,  8), RegisterType.Gpr);
+            Ra = new Register(opCode.Extract(8,  8), RegisterType.Gpr);
+            Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
+            Rc = new Register(opCode.Extract(39, 8), RegisterType.Gpr);
+
+            bool supportsBindless = opCode.Extract(54);
+
+            Type = (ReductionType)opCode.Extract(supportsBindless ? 36 : 51, 3);
+            ByteAddress = opCode.Extract(28);
+            AtomicOp = (AtomicOp)opCode.Extract(29, 4); // Only useful if CAS is not true.
+            Dimensions = (ImageDimensions)opCode.Extract(33, 3);
+            ClampMode = (ClampMode)opCode.Extract(49, 2);
+
+            IsBindless = supportsBindless && !opCode.Extract(51);
+            UseType = !supportsBindless || opCode.Extract(52);
+
+            CompareAndSwap = opCode.Extract(55);
+        }
+    }
+}
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeSured.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeSured.cs
new file mode 100644
index 00000000..57b8ec78
--- /dev/null
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeSured.cs
@@ -0,0 +1,44 @@
+using Ryujinx.Graphics.Shader.Instructions;
+
+namespace Ryujinx.Graphics.Shader.Decoders
+{
+    enum ClampMode
+    {
+        Ignore = 0,
+        Trap = 2
+    }
+
+    class OpCodeSured : OpCodeTextureBase
+    {
+        public Register Ra { get; }
+        public Register Rb { get; }
+        public Register Rc { get; }
+
+        public ReductionType Type { get; }
+        public AtomicOp AtomicOp { get; }
+        public ImageDimensions Dimensions { get; }
+        public ClampMode ClampMode { get; }
+
+        public bool UseType { get; }
+        public bool IsBindless { get; }
+        public bool ByteAddress { get; }
+
+        public new static OpCode Create(InstEmitter emitter, ulong address, long opCode) => new OpCodeSured(emitter, address, opCode);
+
+        public OpCodeSured(InstEmitter emitter, ulong address, long opCode) : base(emitter, address, opCode)
+        {
+            Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
+            Rb = new Register(opCode.Extract(0, 8), RegisterType.Gpr);
+            Rc = new Register(opCode.Extract(39, 8), RegisterType.Gpr);
+
+            Type = (ReductionType)opCode.Extract(20, 3);
+            ByteAddress = opCode.Extract(23);
+            AtomicOp = (AtomicOp)opCode.Extract(24, 3);
+            Dimensions = (ImageDimensions)opCode.Extract(33, 3);
+            ClampMode = (ClampMode)opCode.Extract(49, 2);
+
+            IsBindless = !opCode.Extract(51);
+            UseType = opCode.Extract(52);
+        }
+    }
+}
diff --git a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
index e5bcd7e5..df09d907 100644
--- a/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/OpCodeTable.cs
@@ -209,6 +209,11 @@ namespace Ryujinx.Graphics.Shader.Decoders
             Set("1110111101011x", InstEmit.Sts,     OpCodeMemory.Create);
             Set("11101011000xxx", InstEmit.Suld,    OpCodeImage.Create);
             Set("11101011001xxx", InstEmit.Sust,    OpCodeImage.Create);
+            Set("11101011010xxx", InstEmit.Sured,   OpCodeSured.Create);
+            Set("11101010110xxx", InstEmit.Suatom,  OpCodeSuatom.Create);
+            Set("1110101010xxxx", InstEmit.Suatom,  OpCodeSuatom.Create);
+            Set("11101010011xxx", InstEmit.Suatom,  OpCodeSuatom.Create);
+            Set("1110101000xxxx", InstEmit.Suatom,  OpCodeSuatom.Create);
             Set("1111000011111x", InstEmit.Sync,    OpCodeBranchPop.Create);
             Set("110000xxxx111x", InstEmit.Tex,     OpCodeTex.Create);
             Set("1101111010111x", InstEmit.TexB,    OpCodeTexB.Create);
diff --git a/Ryujinx.Graphics.Shader/Decoders/ReductionType.cs b/Ryujinx.Graphics.Shader/Decoders/ReductionType.cs
index 4c8bd37e..90814c69 100644
--- a/Ryujinx.Graphics.Shader/Decoders/ReductionType.cs
+++ b/Ryujinx.Graphics.Shader/Decoders/ReductionType.cs
@@ -7,6 +7,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
         U64         = 2,
         FP32FtzRn   = 3,
         FP16x2FtzRn = 4,
-        S64         = 5
+        S64         = 5,
+        SD32        = 6,
+        SD64        = 7
     }
 }
\ No newline at end of file