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authorgdkchan <gab.dark.100@gmail.com>2018-02-25 22:14:58 -0300
committergdkchan <gab.dark.100@gmail.com>2018-02-25 22:14:58 -0300
commit950011c90fe28fe9edd8ebe0d0a771f6adcff7a1 (patch)
tree407416f5ee2a157d06ce2fa267671b7e2d1e0946 /Ryujinx.Core/OsHle/Svc
parente174100474fcfe484cc8e93c4db447886096615d (diff)
Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store
Diffstat (limited to 'Ryujinx.Core/OsHle/Svc')
-rw-r--r--Ryujinx.Core/OsHle/Svc/SvcHandler.cs3
1 files changed, 2 insertions, 1 deletions
diff --git a/Ryujinx.Core/OsHle/Svc/SvcHandler.cs b/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
index c5b6da04..ec53f47f 100644
--- a/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
+++ b/Ryujinx.Core/OsHle/Svc/SvcHandler.cs
@@ -1,3 +1,4 @@
+using ChocolArm64.Events;
using ChocolArm64.Memory;
using ChocolArm64.State;
using System;
@@ -62,7 +63,7 @@ namespace Ryujinx.Core.OsHle.Svc
Rng = new Random();
}
- public void SvcCall(object sender, AInstExceptEventArgs e)
+ public void SvcCall(object sender, AInstExceptionEventArgs e)
{
AThreadState ThreadState = (AThreadState)sender;