Implement some ARM32 memory instructions and CMP (#565)

* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)

* Rename some opcode classes and flag masks for consistency

* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations

* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC

* Re-align arm32 instructions on the opcode table

1 files changed, 9 insertions, 1 deletions

diff --git a/ChocolArm64/Translation/ILEmitterCtx.cs b/ChocolArm64/Translation/ILEmitterCtx.cs
index d4bd93ab..b5ebff75 100644
--- a/ChocolArm64/Translation/ILEmitterCtx.cs
+++ b/ChocolArm64/Translation/ILEmitterCtx.cs
@@ -530,7 +530,15 @@ namespace ChocolArm64.Translation
         public void EmitLdflg(int index) => Ldloc(index, IoType.Flag);
         public void EmitStflg(int index)
         {
-            _optOpLastFlagSet = CurrOp;
+            //Set this only if any of the NZCV flag bits were modified.
+            //This is used to ensure that, when emiting a direct IL branch
+            //instruction for compare + branch sequences, we're not expecting
+            //to use comparison values from an old instruction, when in fact
+            //the flags were already overwritten by another instruction further along.
+            if (index >= (int)PState.VBit)
+            {
+                _optOpLastFlagSet = CurrOp;
+            }
 
             Stloc(index, IoType.Flag);
         }