Misc. CPU optimizations (#575)

* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0

* Refactoring

* Add a config entry to enable or disable the reg load/store opt.

* Remove unnecessary register state stores for calls when the callee is know

* Rename IoType to VarType

* Enable tier 0 while fixing some perf issues related to tier 0

* Small tweak -- Compile before adding to the cache, to avoid lags

* Add required config entry

1 files changed, 10 insertions, 10 deletions

diff --git a/ChocolArm64/Translation/ILOpCodeLoad.cs b/ChocolArm64/Translation/ILOpCodeLoad.cs
index c31e06bb..0d11eeaa 100644
--- a/ChocolArm64/Translation/ILOpCodeLoad.cs
+++ b/ChocolArm64/Translation/ILOpCodeLoad.cs
@@ -5,28 +5,28 @@ namespace ChocolArm64.Translation
 {
     struct ILOpCodeLoad : IILEmit
     {
-        public int Index { get; private set; }
+        public int Index { get; }
 
-        public IoType IoType { get; private set; }
+        public VarType VarType { get; }
 
-        public RegisterSize RegisterSize { get; private set; }
+        public RegisterSize RegisterSize { get; }
 
-        public ILOpCodeLoad(int index, IoType ioType, RegisterSize registerSize = 0)
+        public ILOpCodeLoad(int index, VarType varType, RegisterSize registerSize = 0)
         {
             Index        = index;
-            IoType       = ioType;
+            VarType      = varType;
             RegisterSize = registerSize;
         }
 
         public void Emit(ILMethodBuilder context)
         {
-            switch (IoType)
+            switch (VarType)
             {
-                case IoType.Arg: context.Generator.EmitLdarg(Index); break;
+                case VarType.Arg: context.Generator.EmitLdarg(Index); break;
 
-                case IoType.Flag:   EmitLdloc(context, Index, RegisterType.Flag);   break;
-                case IoType.Int:    EmitLdloc(context, Index, RegisterType.Int);    break;
-                case IoType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
+                case VarType.Flag:   EmitLdloc(context, Index, RegisterType.Flag);   break;
+                case VarType.Int:    EmitLdloc(context, Index, RegisterType.Int);    break;
+                case VarType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
             }
         }