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authorgdkchan <gab.dark.100@gmail.com>2019-02-27 23:03:31 -0300
committerjduncanator <1518948+jduncanator@users.noreply.github.com>2019-02-28 13:03:31 +1100
commite21ebbf666f10d39d44a0856e5a44143d3d69d0d (patch)
tree40d25d600ed121eeb397ff24ac7d7d7112b0a079 /ChocolArm64/Translation/ILOpCodeBranch.cs
parent884b4e5fd3c2a54ebb796b7f995c0eda9c4d0038 (diff)
Misc. CPU optimizations (#575)
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
Diffstat (limited to 'ChocolArm64/Translation/ILOpCodeBranch.cs')
-rw-r--r--ChocolArm64/Translation/ILOpCodeBranch.cs10
1 files changed, 5 insertions, 5 deletions
diff --git a/ChocolArm64/Translation/ILOpCodeBranch.cs b/ChocolArm64/Translation/ILOpCodeBranch.cs
index 22b80b5d..9d4e40fa 100644
--- a/ChocolArm64/Translation/ILOpCodeBranch.cs
+++ b/ChocolArm64/Translation/ILOpCodeBranch.cs
@@ -4,18 +4,18 @@ namespace ChocolArm64.Translation
{
struct ILOpCodeBranch : IILEmit
{
- private OpCode _ilOp;
- private ILLabel _label;
+ public OpCode ILOp { get; }
+ public ILLabel Label { get; }
public ILOpCodeBranch(OpCode ilOp, ILLabel label)
{
- _ilOp = ilOp;
- _label = label;
+ ILOp = ilOp;
+ Label = label;
}
public void Emit(ILMethodBuilder context)
{
- context.Generator.Emit(_ilOp, _label.GetLabel(context));
+ context.Generator.Emit(ILOp, Label.GetLabel(context));
}
}
} \ No newline at end of file