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authorgdkchan <gab.dark.100@gmail.com>2019-04-26 01:55:12 -0300
committerjduncanator <1518948+jduncanator@users.noreply.github.com>2019-04-26 14:55:12 +1000
commit8a7d99cdeae2355511d4eb43aefb76d0d886bcf8 (patch)
tree655d33f4db5dc3eb21c9c4ff5867b1179913585a /ChocolArm64/Translation/ILGeneratorEx.cs
parent2b8eac1bcec6d4870776b4f302d9dd7794223642 (diff)
Refactoring and optimization on CPU translation (#661)
* Refactoring and optimization on CPU translation * Remove now unused property * Rename ilBlock -> block (local) * Change equality comparison on RegisterMask for consistency Co-Authored-By: gdkchan <gab.dark.100@gmail.com> * Add back the aggressive inlining attribute to the Synchronize method * Implement IEquatable on the Register struct * Fix identation
Diffstat (limited to 'ChocolArm64/Translation/ILGeneratorEx.cs')
-rw-r--r--ChocolArm64/Translation/ILGeneratorEx.cs8
1 files changed, 0 insertions, 8 deletions
diff --git a/ChocolArm64/Translation/ILGeneratorEx.cs b/ChocolArm64/Translation/ILGeneratorEx.cs
index 318098cc..6b1512d2 100644
--- a/ChocolArm64/Translation/ILGeneratorEx.cs
+++ b/ChocolArm64/Translation/ILGeneratorEx.cs
@@ -117,13 +117,5 @@ namespace ChocolArm64
break;
}
}
-
- public static void EmitLdargSeq(this ILGenerator generator, int count)
- {
- for (int index = 0; index < count; index++)
- {
- generator.EmitLdarg(index);
- }
- }
}
}