Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)

* Change naming convention for Ryujinx project

* Change naming convention for ChocolArm64 project

* Fix NaN

* Remove unneeded this. from Ryujinx project

* Adjust naming from new PRs

* Name changes based on feedback

* How did this get removed?

* Rebasing fix

* Change FP enum case

* Remove prefix from ChocolArm64 classes - Part 1

* Remove prefix from ChocolArm64 classes - Part 2

* Fix alignment from last commit's renaming

* Rename namespaces

* Rename stragglers

* Fix alignment

* Rename OpCode class

* Missed a few

* Adjust alignment

1 files changed, 76 insertions, 0 deletions

diff --git a/ChocolArm64/Translation/ILBlock.cs b/ChocolArm64/Translation/ILBlock.cs
new file mode 100644
index 00000000..d51e8d9e
--- /dev/null
+++ b/ChocolArm64/Translation/ILBlock.cs
@@ -0,0 +1,76 @@
+using System.Collections.Generic;
+
+namespace ChocolArm64.Translation
+{
+    class ILBlock : IILEmit
+    {
+        public long IntInputs    { get; private set; }
+        public long IntOutputs   { get; private set; }
+        public long IntAwOutputs { get; private set; }
+
+        public long VecInputs    { get; private set; }
+        public long VecOutputs   { get; private set; }
+        public long VecAwOutputs { get; private set; }
+
+        public bool HasStateStore { get; private set; }
+
+        public List<IILEmit> IlEmitters { get; private set; }
+
+        public ILBlock Next   { get; set; }
+        public ILBlock Branch { get; set; }
+
+        public ILBlock()
+        {
+            IlEmitters = new List<IILEmit>();
+        }
+
+        public void Add(IILEmit ilEmitter)
+        {
+            if (ilEmitter is ILBarrier)
+            {
+                //Those barriers are used to separate the groups of CIL
+                //opcodes emitted by each ARM instruction.
+                //We can only consider the new outputs for doing input elimination
+                //after all the CIL opcodes used by the instruction being emitted.
+                IntAwOutputs = IntOutputs;
+                VecAwOutputs = VecOutputs;
+            }
+            else if (ilEmitter is IlOpCodeLoad ld && ILEmitter.IsRegIndex(ld.Index))
+            {
+                switch (ld.IoType)
+                {
+                    case IoType.Flag:   IntInputs |= ((1L << ld.Index) << 32) & ~IntAwOutputs; break;
+                    case IoType.Int:    IntInputs |=  (1L << ld.Index)        & ~IntAwOutputs; break;
+                    case IoType.Vector: VecInputs |=  (1L << ld.Index)        & ~VecAwOutputs; break;
+                }
+            }
+            else if (ilEmitter is IlOpCodeStore st)
+            {
+                if (ILEmitter.IsRegIndex(st.Index))
+                {
+                    switch (st.IoType)
+                    {
+                        case IoType.Flag:   IntOutputs |= (1L << st.Index) << 32; break;
+                        case IoType.Int:    IntOutputs |=  1L << st.Index;        break;
+                        case IoType.Vector: VecOutputs |=  1L << st.Index;        break;
+                    }
+                }
+
+                if (st.IoType == IoType.Fields)
+                {
+                    HasStateStore = true;
+                }
+            }
+
+            IlEmitters.Add(ilEmitter);
+        }
+
+        public void Emit(ILEmitter context)
+        {
+            foreach (IILEmit ilEmitter in IlEmitters)
+            {
+                ilEmitter.Emit(context);
+            }
+        }
+    }
+}
\ No newline at end of file