Misc. CPU improvements (#519)

* Fix and simplify TranslatorCache

* Fix some assignment alignments, remove some unused usings

* Changes to ILEmitter, separate it from ILEmitterCtx

* Rename ILEmitter to ILMethodBuilder

* Rename LdrLit and *_Fix opcodes

* Revert TranslatorCache impl to the more performant one, fix a few issues with it

* Allow EmitOpCode to be called even after everything has been emitted

* Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point

* Remove unneeded temp use

* Add missing exit call on TestExclusive

* Use better hash

* Implement the == and != operators

1 files changed, 19 insertions, 21 deletions

diff --git a/ChocolArm64/Translation/ILBlock.cs b/ChocolArm64/Translation/ILBlock.cs
index d51e8d9e..13657901 100644
--- a/ChocolArm64/Translation/ILBlock.cs
+++ b/ChocolArm64/Translation/ILBlock.cs
@@ -14,19 +14,21 @@ namespace ChocolArm64.Translation
 
         public bool HasStateStore { get; private set; }
 
-        public List<IILEmit> IlEmitters { get; private set; }
+        private List<IILEmit> _emitters;
+
+        public int Count => _emitters.Count;
 
         public ILBlock Next   { get; set; }
         public ILBlock Branch { get; set; }
 
         public ILBlock()
         {
-            IlEmitters = new List<IILEmit>();
+            _emitters = new List<IILEmit>();
         }
 
-        public void Add(IILEmit ilEmitter)
+        public void Add(IILEmit emitter)
         {
-            if (ilEmitter is ILBarrier)
+            if (emitter is ILBarrier)
             {
                 //Those barriers are used to separate the groups of CIL
                 //opcodes emitted by each ARM instruction.
@@ -35,7 +37,7 @@ namespace ChocolArm64.Translation
                 IntAwOutputs = IntOutputs;
                 VecAwOutputs = VecOutputs;
             }
-            else if (ilEmitter is IlOpCodeLoad ld && ILEmitter.IsRegIndex(ld.Index))
+            else if (emitter is ILOpCodeLoad ld && ILMethodBuilder.IsRegIndex(ld.Index))
             {
                 switch (ld.IoType)
                 {
@@ -44,30 +46,26 @@ namespace ChocolArm64.Translation
                     case IoType.Vector: VecInputs |=  (1L << ld.Index)        & ~VecAwOutputs; break;
                 }
             }
-            else if (ilEmitter is IlOpCodeStore st)
+            else if (emitter is ILOpCodeStore st && ILMethodBuilder.IsRegIndex(st.Index))
             {
-                if (ILEmitter.IsRegIndex(st.Index))
-                {
-                    switch (st.IoType)
-                    {
-                        case IoType.Flag:   IntOutputs |= (1L << st.Index) << 32; break;
-                        case IoType.Int:    IntOutputs |=  1L << st.Index;        break;
-                        case IoType.Vector: VecOutputs |=  1L << st.Index;        break;
-                    }
-                }
-
-                if (st.IoType == IoType.Fields)
+                switch (st.IoType)
                 {
-                    HasStateStore = true;
+                    case IoType.Flag:   IntOutputs |= (1L << st.Index) << 32; break;
+                    case IoType.Int:    IntOutputs |=  1L << st.Index;        break;
+                    case IoType.Vector: VecOutputs |=  1L << st.Index;        break;
                 }
             }
+            else if (emitter is ILOpCodeStoreState)
+            {
+                HasStateStore = true;
+            }
 
-            IlEmitters.Add(ilEmitter);
+            _emitters.Add(emitter);
         }
 
-        public void Emit(ILEmitter context)
+        public void Emit(ILMethodBuilder context)
         {
-            foreach (IILEmit ilEmitter in IlEmitters)
+            foreach (IILEmit ilEmitter in _emitters)
             {
                 ilEmitter.Emit(context);
             }