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| author | gdkchan <gab.dark.100@gmail.com> | 2019-01-24 23:59:53 -0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-24 23:59:53 -0200 |
| commit | 36b9ab0e48b6893c057a954e1ef3181b452add1c (patch) | |
| tree | 16a4ae56019b55d0cb61f1aa105481933ada733e /ChocolArm64/State/Register.cs | |
| parent | 72157e03eb09d4fb5d6d004efc2d13d3194e8c90 (diff) | |
Add ARM32 support on the translator (#561)
* Remove ARM32 interpreter and add ARM32 support on the translator
* Nits.
* Rename Cond -> Condition
* Align code again
* Rename Data to Alu
* Enable ARM32 support and handle undefined instructions
* Use the IsThumb method to check if its a thumb opcode
* Remove another 32-bits check
Diffstat (limited to 'ChocolArm64/State/Register.cs')
| -rw-r--r-- | ChocolArm64/State/Register.cs | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/ChocolArm64/State/Register.cs b/ChocolArm64/State/Register.cs index ea29e7b6..34588231 100644 --- a/ChocolArm64/State/Register.cs +++ b/ChocolArm64/State/Register.cs @@ -43,6 +43,8 @@ namespace ChocolArm64.State { switch ((PState)Index) { + case PState.TBit: return GetField(nameof(CpuThreadState.Thumb)); + case PState.VBit: return GetField(nameof(CpuThreadState.Overflow)); case PState.CBit: return GetField(nameof(CpuThreadState.Carry)); case PState.ZBit: return GetField(nameof(CpuThreadState.Zero)); |