diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2019-05-31 00:51:39 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2019-05-30 19:51:39 -0300 |
| commit | ffbfbb554965651194a58ca92a3a5db195cdc7ed (patch) | |
| tree | c5fffc0a958daf9499feb4de3a42bae5467134ce /ChocolArm64/OpCodeTable.cs | |
| parent | e7be60b6c6dab16ad954b00122190e03778b8e70 (diff) | |
Add FCVT <Hd>, <Sn> and FCVT <Sd>, <Hn> Inst.; add Tests. (#692)
* Update OpCodeTable.cs
* Update InstEmitSimdCvt.cs
* Update CpuTestSimd.cs
* Address PR feedback.
Diffstat (limited to 'ChocolArm64/OpCodeTable.cs')
| -rw-r--r-- | ChocolArm64/OpCodeTable.cs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ChocolArm64/OpCodeTable.cs b/ChocolArm64/OpCodeTable.cs index a1bbd4bc..2200faef 100644 --- a/ChocolArm64/OpCodeTable.cs +++ b/ChocolArm64/OpCodeTable.cs @@ -296,7 +296,7 @@ namespace ChocolArm64 SetA64("000111100x1xxxxx001000xxxxx0x000", InstEmit.Fcmp_S, typeof(OpCodeSimdReg64)); SetA64("000111100x1xxxxx001000xxxxx1x000", InstEmit.Fcmpe_S, typeof(OpCodeSimdReg64)); SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", InstEmit.Fcsel_S, typeof(OpCodeSimdFcond64)); - SetA64("000111100x10001xx10000xxxxxxxxxx", InstEmit.Fcvt_S, typeof(OpCodeSimd64)); + SetA64("00011110xx10001xx10000xxxxxxxxxx", InstEmit.Fcvt_S, typeof(OpCodeSimd64)); SetA64("x00111100x100100000000xxxxxxxxxx", InstEmit.Fcvtas_Gp, typeof(OpCodeSimdCvt64)); SetA64("x00111100x100101000000xxxxxxxxxx", InstEmit.Fcvtau_Gp, typeof(OpCodeSimdCvt64)); SetA64("0x0011100x100001011110xxxxxxxxxx", InstEmit.Fcvtl_V, typeof(OpCodeSimd64)); |