diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2019-04-26 01:55:12 -0300 |
|---|---|---|
| committer | jduncanator <1518948+jduncanator@users.noreply.github.com> | 2019-04-26 14:55:12 +1000 |
| commit | 8a7d99cdeae2355511d4eb43aefb76d0d886bcf8 (patch) | |
| tree | 655d33f4db5dc3eb21c9c4ff5867b1179913585a /ChocolArm64/IntermediateRepresentation/OperationType.cs | |
| parent | 2b8eac1bcec6d4870776b4f302d9dd7794223642 (diff) | |
Refactoring and optimization on CPU translation (#661)
* Refactoring and optimization on CPU translation
* Remove now unused property
* Rename ilBlock -> block (local)
* Change equality comparison on RegisterMask for consistency
Co-Authored-By: gdkchan <gab.dark.100@gmail.com>
* Add back the aggressive inlining attribute to the Synchronize method
* Implement IEquatable on the Register struct
* Fix identation
Diffstat (limited to 'ChocolArm64/IntermediateRepresentation/OperationType.cs')
| -rw-r--r-- | ChocolArm64/IntermediateRepresentation/OperationType.cs | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/ChocolArm64/IntermediateRepresentation/OperationType.cs b/ChocolArm64/IntermediateRepresentation/OperationType.cs new file mode 100644 index 00000000..644f1716 --- /dev/null +++ b/ChocolArm64/IntermediateRepresentation/OperationType.cs @@ -0,0 +1,18 @@ +namespace ChocolArm64.IntermediateRepresentation +{ + enum OperationType + { + Call, + CallVirtual, + IL, + ILBranch, + LoadArgument, + LoadConstant, + LoadContext, + LoadField, + LoadLocal, + MarkLabel, + StoreContext, + StoreLocal + } +}
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