diff options
| author | Alex Barney <thealexbarney@gmail.com> | 2018-10-30 19:43:02 -0600 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-10-30 22:43:02 -0300 |
| commit | 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d (patch) | |
| tree | 0c97425aeb311c142bc92a6fcc503cb2c07d4376 /ChocolArm64/Instructions32/A32InstInterpretHelper.cs | |
| parent | 5a87e58183578f5b84ca8d01cbb76aed11820f78 (diff) | |
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
* Change naming convention for Ryujinx project
* Change naming convention for ChocolArm64 project
* Fix NaN
* Remove unneeded this. from Ryujinx project
* Adjust naming from new PRs
* Name changes based on feedback
* How did this get removed?
* Rebasing fix
* Change FP enum case
* Remove prefix from ChocolArm64 classes - Part 1
* Remove prefix from ChocolArm64 classes - Part 2
* Fix alignment from last commit's renaming
* Rename namespaces
* Rename stragglers
* Fix alignment
* Rename OpCode class
* Missed a few
* Adjust alignment
Diffstat (limited to 'ChocolArm64/Instructions32/A32InstInterpretHelper.cs')
| -rw-r--r-- | ChocolArm64/Instructions32/A32InstInterpretHelper.cs | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/ChocolArm64/Instructions32/A32InstInterpretHelper.cs b/ChocolArm64/Instructions32/A32InstInterpretHelper.cs new file mode 100644 index 00000000..b08e1298 --- /dev/null +++ b/ChocolArm64/Instructions32/A32InstInterpretHelper.cs @@ -0,0 +1,65 @@ +using ChocolArm64.Decoders; +using ChocolArm64.State; +using System; + +namespace ChocolArm64.Instructions32 +{ + static class A32InstInterpretHelper + { + public static bool IsConditionTrue(CpuThreadState state, Cond cond) + { + switch (cond) + { + case Cond.Eq: return state.Zero; + case Cond.Ne: return !state.Zero; + case Cond.GeUn: return state.Carry; + case Cond.LtUn: return !state.Carry; + case Cond.Mi: return state.Negative; + case Cond.Pl: return !state.Negative; + case Cond.Vs: return state.Overflow; + case Cond.Vc: return !state.Overflow; + case Cond.GtUn: return state.Carry && !state.Zero; + case Cond.LeUn: return !state.Carry && state.Zero; + case Cond.Ge: return state.Negative == state.Overflow; + case Cond.Lt: return state.Negative != state.Overflow; + case Cond.Gt: return state.Negative == state.Overflow && !state.Zero; + case Cond.Le: return state.Negative != state.Overflow && state.Zero; + } + + return true; + } + + public unsafe static uint GetReg(CpuThreadState state, int reg) + { + if ((uint)reg > 15) + { + throw new ArgumentOutOfRangeException(nameof(reg)); + } + + fixed (uint* ptr = &state.R0) + { + return *(ptr + reg); + } + } + + public unsafe static void SetReg(CpuThreadState state, int reg, uint value) + { + if ((uint)reg > 15) + { + throw new ArgumentOutOfRangeException(nameof(reg)); + } + + fixed (uint* ptr = &state.R0) + { + *(ptr + reg) = value; + } + } + + public static uint GetPc(CpuThreadState state) + { + //Due to the old fetch-decode-execute pipeline of old ARM CPUs, + //the PC is 4 or 8 bytes (2 instructions) ahead of the current instruction. + return state.R15 + (state.Thumb ? 2U : 4U); + } + } +}
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