diff options
| author | Alex Barney <thealexbarney@gmail.com> | 2018-10-30 19:43:02 -0600 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-10-30 22:43:02 -0300 |
| commit | 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d (patch) | |
| tree | 0c97425aeb311c142bc92a6fcc503cb2c07d4376 /ChocolArm64/Instructions32/A32InstInterpretFlow.cs | |
| parent | 5a87e58183578f5b84ca8d01cbb76aed11820f78 (diff) | |
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
* Change naming convention for Ryujinx project
* Change naming convention for ChocolArm64 project
* Fix NaN
* Remove unneeded this. from Ryujinx project
* Adjust naming from new PRs
* Name changes based on feedback
* How did this get removed?
* Rebasing fix
* Change FP enum case
* Remove prefix from ChocolArm64 classes - Part 1
* Remove prefix from ChocolArm64 classes - Part 2
* Fix alignment from last commit's renaming
* Rename namespaces
* Rename stragglers
* Fix alignment
* Rename OpCode class
* Missed a few
* Adjust alignment
Diffstat (limited to 'ChocolArm64/Instructions32/A32InstInterpretFlow.cs')
| -rw-r--r-- | ChocolArm64/Instructions32/A32InstInterpretFlow.cs | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/ChocolArm64/Instructions32/A32InstInterpretFlow.cs b/ChocolArm64/Instructions32/A32InstInterpretFlow.cs new file mode 100644 index 00000000..cdf7e4c6 --- /dev/null +++ b/ChocolArm64/Instructions32/A32InstInterpretFlow.cs @@ -0,0 +1,70 @@ +using ChocolArm64.Decoders; +using ChocolArm64.Decoders32; +using ChocolArm64.Memory; +using ChocolArm64.State; + +using static ChocolArm64.Instructions32.A32InstInterpretHelper; + +namespace ChocolArm64.Instructions32 +{ + static partial class A32InstInterpret + { + public static void B(CpuThreadState state, MemoryManager memory, OpCode64 opCode) + { + A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode; + + if (IsConditionTrue(state, op.Cond)) + { + BranchWritePc(state, GetPc(state) + (uint)op.Imm); + } + } + + public static void Bl(CpuThreadState state, MemoryManager memory, OpCode64 opCode) + { + Blx(state, memory, opCode, false); + } + + public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode) + { + Blx(state, memory, opCode, true); + } + + public static void Blx(CpuThreadState state, MemoryManager memory, OpCode64 opCode, bool x) + { + A32OpCodeBImmAl op = (A32OpCodeBImmAl)opCode; + + if (IsConditionTrue(state, op.Cond)) + { + uint pc = GetPc(state); + + if (state.Thumb) + { + state.R14 = pc | 1; + } + else + { + state.R14 = pc - 4U; + } + + if (x) + { + state.Thumb = !state.Thumb; + } + + if (!state.Thumb) + { + pc &= ~3U; + } + + BranchWritePc(state, pc + (uint)op.Imm); + } + } + + private static void BranchWritePc(CpuThreadState state, uint pc) + { + state.R15 = state.Thumb + ? pc & ~1U + : pc & ~3U; + } + } +}
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