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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-11-18 03:41:16 +0100
committergdkchan <gab.dark.100@gmail.com>2018-11-18 00:41:16 -0200
commite603b7afbcdff0fc732304872f5a65d410c601f9 (patch)
treed1949402bc6c6edd5a3d6e2ea40d9033a3d2f654 /ChocolArm64/Instructions/SoftFloat.cs
parentb7613dd4b8a535d028ae180ee3a4b574abe4e3e0 (diff)
Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Update InstEmitSimdCmp.cs * Update SoftFloat.cs * Update InstEmitAluHelper.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdHelper.cs * Update VectorHelper.cs * Update InstEmitSimdCvt.cs * Update InstEmitSimdArithmetic.cs * Update CpuTestSimd.cs * Update InstEmitSimdArithmetic.cs * Update OpCodeTable.cs * Update InstEmitSimdArithmetic.cs * Update InstEmitSimdCmp.cs * Update InstEmitSimdCvt.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Create CpuTestSimdFcond.cs * Update OpCodeTable.cs * Update InstEmitSimdMove.cs * Update CpuTestSimdIns.cs * Create CpuTestSimdExt.cs * Nit. * Update PackageReference.
Diffstat (limited to 'ChocolArm64/Instructions/SoftFloat.cs')
-rw-r--r--ChocolArm64/Instructions/SoftFloat.cs74
1 files changed, 74 insertions, 0 deletions
diff --git a/ChocolArm64/Instructions/SoftFloat.cs b/ChocolArm64/Instructions/SoftFloat.cs
index 72b39efc..2af8afbd 100644
--- a/ChocolArm64/Instructions/SoftFloat.cs
+++ b/ChocolArm64/Instructions/SoftFloat.cs
@@ -789,6 +789,43 @@ namespace ChocolArm64.Instructions
return result;
}
+ public static int FPCompare(float value1, float value2, bool signalNaNs, CpuThreadState state)
+ {
+ Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
+
+ value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
+ value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
+
+ int result;
+
+ if (type1 == FpType.SNaN || type1 == FpType.QNaN || type2 == FpType.SNaN || type2 == FpType.QNaN)
+ {
+ result = 0b0011;
+
+ if (type1 == FpType.SNaN || type2 == FpType.SNaN || signalNaNs)
+ {
+ FPProcessException(FpExc.InvalidOp, state);
+ }
+ }
+ else
+ {
+ if (value1 == value2)
+ {
+ result = 0b0110;
+ }
+ else if (value1 < value2)
+ {
+ result = 0b1000;
+ }
+ else
+ {
+ result = 0b0010;
+ }
+ }
+
+ return result;
+ }
+
public static float FPDiv(float value1, float value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat32.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");
@@ -1584,6 +1621,43 @@ namespace ChocolArm64.Instructions
return result;
}
+ public static int FPCompare(double value1, double value2, bool signalNaNs, CpuThreadState state)
+ {
+ Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPCompare: state.Fpcr = 0x{state.Fpcr:X8}");
+
+ value1 = value1.FPUnpack(out FpType type1, out bool sign1, out _, state);
+ value2 = value2.FPUnpack(out FpType type2, out bool sign2, out _, state);
+
+ int result;
+
+ if (type1 == FpType.SNaN || type1 == FpType.QNaN || type2 == FpType.SNaN || type2 == FpType.QNaN)
+ {
+ result = 0b0011;
+
+ if (type1 == FpType.SNaN || type2 == FpType.SNaN || signalNaNs)
+ {
+ FPProcessException(FpExc.InvalidOp, state);
+ }
+ }
+ else
+ {
+ if (value1 == value2)
+ {
+ result = 0b0110;
+ }
+ else if (value1 < value2)
+ {
+ result = 0b1000;
+ }
+ else
+ {
+ result = 0b0010;
+ }
+ }
+
+ return result;
+ }
+
public static double FPDiv(double value1, double value2, CpuThreadState state)
{
Debug.WriteLineIf(state.Fpcr != 0, $"SoftFloat64.FPDiv: state.Fpcr = 0x{state.Fpcr:X8}");