diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-12-02 01:34:43 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-12-01 22:34:43 -0200 |
| commit | ad00fd02442cf9c0f00c4562635738042b521efa (patch) | |
| tree | cf1e9607e41f616d2c0ad171406fc1d271d45456 /ChocolArm64/Instructions/InstEmitSimdArithmetic.cs | |
| parent | 9b22e8af5ee3e0896fc5f464022579ef0713e504 (diff) | |
Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs
* Update InstEmitSimdShift.cs
* Update SoftFallback.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFallback.cs
* Update Optimizations.cs
* Update InstEmitSimdLogical.cs
* Update InstEmitSimdArithmetic.cs
Diffstat (limited to 'ChocolArm64/Instructions/InstEmitSimdArithmetic.cs')
| -rw-r--r-- | ChocolArm64/Instructions/InstEmitSimdArithmetic.cs | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/ChocolArm64/Instructions/InstEmitSimdArithmetic.cs b/ChocolArm64/Instructions/InstEmitSimdArithmetic.cs index c05e9f94..df84596b 100644 --- a/ChocolArm64/Instructions/InstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instructions/InstEmitSimdArithmetic.cs @@ -1638,7 +1638,34 @@ namespace ChocolArm64.Instructions public static void Neg_V(ILEmitterCtx context) { - EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); + if (Optimizations.UseSse2) + { + OpCodeSimd64 op = (OpCodeSimd64)context.CurrOp; + + Type[] typesSub = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] }; + + string[] namesSzv = new string[] { nameof(VectorHelper.VectorSByteZero), + nameof(VectorHelper.VectorInt16Zero), + nameof(VectorHelper.VectorInt32Zero), + nameof(VectorHelper.VectorInt64Zero) }; + + VectorHelper.EmitCall(context, namesSzv[op.Size]); + + EmitLdvecWithSignedCast(context, op.Rn, op.Size); + + context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.Subtract), typesSub)); + + EmitStvecWithSignedCast(context, op.Rd, op.Size); + + if (op.RegisterSize == RegisterSize.Simd64) + { + EmitVectorZeroUpper(context, op.Rd); + } + } + else + { + EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); + } } public static void Raddhn_V(ILEmitterCtx context) |
