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| author | gdkchan <gab.dark.100@gmail.com> | 2019-02-27 23:03:31 -0300 |
|---|---|---|
| committer | jduncanator <1518948+jduncanator@users.noreply.github.com> | 2019-02-28 13:03:31 +1100 |
| commit | e21ebbf666f10d39d44a0856e5a44143d3d69d0d (patch) | |
| tree | 40d25d600ed121eeb397ff24ac7d7d7112b0a079 /ChocolArm64/Instructions/InstEmitFlow.cs | |
| parent | 884b4e5fd3c2a54ebb796b7f995c0eda9c4d0038 (diff) | |
Misc. CPU optimizations (#575)
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0
* Refactoring
* Add a config entry to enable or disable the reg load/store opt.
* Remove unnecessary register state stores for calls when the callee is know
* Rename IoType to VarType
* Enable tier 0 while fixing some perf issues related to tier 0
* Small tweak -- Compile before adding to the cache, to avoid lags
* Add required config entry
Diffstat (limited to 'ChocolArm64/Instructions/InstEmitFlow.cs')
| -rw-r--r-- | ChocolArm64/Instructions/InstEmitFlow.cs | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/ChocolArm64/Instructions/InstEmitFlow.cs b/ChocolArm64/Instructions/InstEmitFlow.cs index a842dca9..5eae89cc 100644 --- a/ChocolArm64/Instructions/InstEmitFlow.cs +++ b/ChocolArm64/Instructions/InstEmitFlow.cs @@ -39,7 +39,6 @@ namespace ChocolArm64.Instructions context.EmitLdc_I(op.Position + 4); context.EmitStint(RegisterAlias.Lr); - context.EmitStoreState(); EmitCall(context, op.Imm); } @@ -60,6 +59,8 @@ namespace ChocolArm64.Instructions { OpCodeBReg64 op = (OpCodeBReg64)context.CurrOp; + context.HasIndirectJump = true; + context.EmitStoreState(); context.EmitLdintzr(op.Rn); |