diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-11-18 03:41:16 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-11-18 00:41:16 -0200 |
| commit | e603b7afbcdff0fc732304872f5a65d410c601f9 (patch) | |
| tree | d1949402bc6c6edd5a3d6e2ea40d9033a3d2f654 /ChocolArm64/Instructions/InstEmitAluHelper.cs | |
| parent | b7613dd4b8a535d028ae180ee3a4b574abe4e3e0 (diff) | |
Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update InstEmitSimdCmp.cs
* Update SoftFloat.cs
* Update InstEmitAluHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update VectorHelper.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update InstEmitSimdArithmetic.cs
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdCmp.cs
* Update InstEmitSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Create CpuTestSimdFcond.cs
* Update OpCodeTable.cs
* Update InstEmitSimdMove.cs
* Update CpuTestSimdIns.cs
* Create CpuTestSimdExt.cs
* Nit.
* Update PackageReference.
Diffstat (limited to 'ChocolArm64/Instructions/InstEmitAluHelper.cs')
| -rw-r--r-- | ChocolArm64/Instructions/InstEmitAluHelper.cs | 29 |
1 files changed, 19 insertions, 10 deletions
diff --git a/ChocolArm64/Instructions/InstEmitAluHelper.cs b/ChocolArm64/Instructions/InstEmitAluHelper.cs index 613dd234..97c50564 100644 --- a/ChocolArm64/Instructions/InstEmitAluHelper.cs +++ b/ChocolArm64/Instructions/InstEmitAluHelper.cs @@ -190,23 +190,32 @@ namespace ChocolArm64.Instructions } } - public static void EmitSetNzcv(ILEmitterCtx context, int nzcv) + public static void EmitSetNzcv(ILEmitterCtx context) { - context.EmitLdc_I4((nzcv >> 0) & 1); - + context.Emit(OpCodes.Dup); + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.And); context.EmitStflg((int)PState.VBit); - context.EmitLdc_I4((nzcv >> 1) & 1); - + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.Shr); + context.Emit(OpCodes.Dup); + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.And); context.EmitStflg((int)PState.CBit); - context.EmitLdc_I4((nzcv >> 2) & 1); - + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.Shr); + context.Emit(OpCodes.Dup); + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.And); context.EmitStflg((int)PState.ZBit); - context.EmitLdc_I4((nzcv >> 3) & 1); - + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.Shr); + context.Emit(OpCodes.Ldc_I4_1); + context.Emit(OpCodes.And); context.EmitStflg((int)PState.NBit); } } -}
\ No newline at end of file +} |