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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-09-08 19:24:29 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-09-08 14:24:29 -0300 |
| commit | a0c78f792012cdea060444d7cb6a36dbabb04d52 (patch) | |
| tree | d0c517047dac5fc96c04135ccfb07ef5d2db1622 /ChocolArm64/Instruction/ASoftFallback.cs | |
| parent | ca1e37a29553f97ecf574fb3678422dd93a2b91d (diff) | |
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update AOpCodeSimdShImm.cs
* Update ABitUtils.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdShImm.cs
* Create CpuTestSimdRegElem.cs
* Address PR feedback.
* Nit.
* Nit.
Diffstat (limited to 'ChocolArm64/Instruction/ASoftFallback.cs')
| -rw-r--r-- | ChocolArm64/Instruction/ASoftFallback.cs | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs index 0ae84ab2..a7bc1085 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/ASoftFallback.cs @@ -16,6 +16,92 @@ namespace ChocolArm64.Instruction Context.EmitCall(typeof(ASoftFallback), MthdName); } +#region "ShrImm_64" + public static long SignedShrImm_64(long Value, long RoundConst, int Shift) + { + if (RoundConst == 0L) + { + if (Shift <= 63) + { + return Value >> Shift; + } + else /* if (Shift == 64) */ + { + if (Value < 0L) + { + return -1L; + } + else + { + return 0L; + } + } + } + else /* if (RoundConst == 1L << (Shift - 1)) */ + { + if (Shift <= 63) + { + long Add = Value + RoundConst; + + if ((~Value & (Value ^ Add)) < 0L) + { + return (long)((ulong)Add >> Shift); + } + else + { + return Add >> Shift; + } + } + else /* if (Shift == 64) */ + { + return 0L; + } + } + } + + public static ulong UnsignedShrImm_64(ulong Value, long RoundConst, int Shift) + { + if (RoundConst == 0L) + { + if (Shift <= 63) + { + return Value >> Shift; + } + else /* if (Shift == 64) */ + { + return 0UL; + } + } + else /* if (RoundConst == 1L << (Shift - 1)) */ + { + ulong Add = Value + (ulong)RoundConst; + + if ((Add < Value) && (Add < (ulong)RoundConst)) + { + if (Shift <= 63) + { + return (Add >> Shift) | (0x8000000000000000UL >> (Shift - 1)); + } + else /* if (Shift == 64) */ + { + return 1UL; + } + } + else + { + if (Shift <= 63) + { + return Add >> Shift; + } + else /* if (Shift == 64) */ + { + return 0UL; + } + } + } + } +#endregion + #region "Saturating" public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State) { |