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authorgdkchan <gab.dark.100@gmail.com>2018-03-06 21:36:49 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-06 21:36:49 -0300
commitbe0e4007dc92e24a77bdc36a40d2450c41d9b560 (patch)
tree66fa62381cba101e336000865a1c3e561f3298d5 /ChocolArm64/Instruction/AInstEmitSimdMove.cs
parent4f177c9ee7452274f5e792349e9b443d78a27816 (diff)
Add SMLAL (vector), fix EXT instruction
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdMove.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdMove.cs13
1 files changed, 8 insertions, 5 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
index a4e53370..3f427ad8 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
@@ -63,15 +63,18 @@ namespace ChocolArm64.Instruction
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+ int Position = Op.Imm4;
+
for (int Index = 0; Index < Bytes; Index++)
{
- int Position = Op.Imm4 + Index;
-
- int Reg = Position < Bytes ? Op.Rn : Op.Rm;
+ int Reg = Op.Imm4 + Index < Bytes ? Op.Rn : Op.Rm;
- Position &= Bytes - 1;
+ if (Position == Bytes)
+ {
+ Position = 0;
+ }
- EmitVectorExtractZx(Context, Reg, Position, 0);
+ EmitVectorExtractZx(Context, Reg, Position++, 0);
EmitVectorInsert(Context, Op.Rd, Index, 0);
}