diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 17:37:31 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 17:37:31 -0300 |
| commit | 916540ff41446643a952fe7612aed16bae3fd7d8 (patch) | |
| tree | fe6358cfcee8924d0f9dbf2755b0efde259923e5 /ChocolArm64/Instruction/AInstEmitSimdMove.cs | |
| parent | 76ac31add656c71f9cfb3307f5863cc98c8d1467 (diff) | |
Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdMove.cs')
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdMove.cs | 21 |
1 files changed, 13 insertions, 8 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs index 3f427ad8..80f41787 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs @@ -61,6 +61,9 @@ namespace ChocolArm64.Instruction { AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp; + Context.EmitLdvec(Op.Rd); + Context.EmitStvectmp(); + int Bytes = Context.CurrOp.GetBitsCount() >> 3; int Position = Op.Imm4; @@ -75,10 +78,12 @@ namespace ChocolArm64.Instruction } EmitVectorExtractZx(Context, Reg, Position++, 0); - - EmitVectorInsert(Context, Op.Rd, Index, 0); + EmitVectorInsertTmp(Context, Index, 0); } + Context.EmitLdvectmp(); + Context.EmitStvec(Op.Rd); + if (Op.RegisterSize == ARegisterSize.SIMD64) { EmitVectorZeroUpper(Context, Op.Rd); @@ -113,7 +118,7 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, Op.Rn, 0, 3); - EmitIntZeroHigherIfNeeded(Context); + EmitIntZeroUpperIfNeeded(Context); Context.EmitStintzr(Op.Rd); } @@ -124,7 +129,7 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(Context, Op.Rn, 1, 3); - EmitIntZeroHigherIfNeeded(Context); + EmitIntZeroUpperIfNeeded(Context); Context.EmitStintzr(Op.Rd); } @@ -135,7 +140,7 @@ namespace ChocolArm64.Instruction Context.EmitLdintzr(Op.Rn); - EmitIntZeroHigherIfNeeded(Context); + EmitIntZeroUpperIfNeeded(Context); EmitScalarSet(Context, Op.Rd, 3); } @@ -146,7 +151,7 @@ namespace ChocolArm64.Instruction Context.EmitLdintzr(Op.Rn); - EmitIntZeroHigherIfNeeded(Context); + EmitIntZeroUpperIfNeeded(Context); EmitVectorInsert(Context, Op.Rd, 1, 3); } @@ -301,7 +306,7 @@ namespace ChocolArm64.Instruction EmitVectorZip(Context, Part: 1); } - private static void EmitIntZeroHigherIfNeeded(AILEmitterCtx Context) + private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context) { if (Context.CurrOp.RegisterSize == ARegisterSize.Int32) { @@ -322,7 +327,7 @@ namespace ChocolArm64.Instruction for (int Index = 0; Index < Elems; Index++) { int Elem = Part + ((Index & (Half - 1)) << 1); - + EmitVectorExtractZx(Context, Index < Half ? Op.Rn : Op.Rm, Elem, Op.Size); EmitVectorInsert(Context, Op.Rd, Index, Op.Size); |