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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-04-12 16:52:00 +0200
committergdkchan <gab.dark.100@gmail.com>2018-04-12 11:52:00 -0300
commit262b5b80541d23ed248d5b4f2220a479a35d5969 (patch)
tree0ba1d4b453dcffe7c00b7354264e4ac4d91317dc /ChocolArm64/Instruction/AInstEmitSimdMove.cs
parent9227b0ea59c6f5f5233bbedf633dc68097275129 (diff)
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)
* Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdMove.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdMove.cs35
1 files changed, 34 insertions, 1 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
index 80f41787..20268d58 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdMove.cs
@@ -256,6 +256,16 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Op.Rd);
}
+ public static void Trn1_V(AILEmitterCtx Context)
+ {
+ EmitVectorTranspose(Context, Part: 0);
+ }
+
+ public static void Trn2_V(AILEmitterCtx Context)
+ {
+ EmitVectorTranspose(Context, Part: 1);
+ }
+
public static void Umov_S(AILEmitterCtx Context)
{
AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
@@ -315,6 +325,29 @@ namespace ChocolArm64.Instruction
}
}
+ private static void EmitVectorTranspose(AILEmitterCtx Context, int Part)
+ {
+ AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
+
+ int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+ int Elems = Bytes >> Op.Size;
+
+ for (int Index = 0; Index < Elems; Index++)
+ {
+ int Elem = (Index & ~1) + Part;
+
+ EmitVectorExtractZx(Context, (Index & 1) == 0 ? Op.Rn : Op.Rm, Elem, Op.Size);
+
+ EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ }
+
+ if (Op.RegisterSize == ARegisterSize.SIMD64)
+ {
+ EmitVectorZeroUpper(Context, Op.Rd);
+ }
+ }
+
private static void EmitVectorUnzip(AILEmitterCtx Context, int Part)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
@@ -363,4 +396,4 @@ namespace ChocolArm64.Instruction
}
}
}
-} \ No newline at end of file
+}