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authorgdkchan <gab.dark.100@gmail.com>2018-03-16 00:42:44 -0300
committergdkchan <gab.dark.100@gmail.com>2018-03-16 00:42:44 -0300
commit4940cf0ea58c77c8666d76abdfc35c6380efed4c (patch)
tree63f3a364c0259435c6a32d362eacf5590231d115 /ChocolArm64/Instruction/AInstEmitSimdLogical.cs
parent88c6160c62b000d155a829b23e6207d78b7dccfa (diff)
Add BFI instruction, even more audout fixes
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdLogical.cs')
-rw-r--r--ChocolArm64/Instruction/AInstEmitSimdLogical.cs30
1 files changed, 30 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
index 5b71a0bb..8fd8ea4d 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdLogical.cs
@@ -32,6 +32,36 @@ namespace ChocolArm64.Instruction
});
}
+ public static void Bif_V(AILEmitterCtx Context)
+ {
+ AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
+
+ int Bytes = Context.CurrOp.GetBitsCount() >> 3;
+
+ for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
+ {
+ EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
+ EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
+
+ Context.Emit(OpCodes.Xor);
+
+ EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
+
+ Context.Emit(OpCodes.And);
+
+ EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
+
+ Context.Emit(OpCodes.Xor);
+
+ EmitVectorInsert(Context, Op.Rd, Index, Op.Size);
+ }
+
+ if (Op.RegisterSize == ARegisterSize.SIMD64)
+ {
+ EmitVectorZeroUpper(Context, Op.Rd);
+ }
+ }
+
public static void Bsl_V(AILEmitterCtx Context)
{
EmitVectorTernaryOpZx(Context, () =>