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| author | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 17:37:31 -0300 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-03-30 17:37:31 -0300 |
| commit | 916540ff41446643a952fe7612aed16bae3fd7d8 (patch) | |
| tree | fe6358cfcee8924d0f9dbf2755b0efde259923e5 /ChocolArm64/Instruction/AInstEmitSimdHelper.cs | |
| parent | 76ac31add656c71f9cfb3307f5863cc98c8d1467 (diff) | |
Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)
Diffstat (limited to 'ChocolArm64/Instruction/AInstEmitSimdHelper.cs')
| -rw-r--r-- | ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index d8642e99..9a749ec6 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -447,6 +447,9 @@ namespace ChocolArm64.Instruction { AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + Context.EmitLdvec(Op.Rd); + Context.EmitStvectmp(); + int Elems = 8 >> Op.Size; int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0; @@ -489,6 +492,9 @@ namespace ChocolArm64.Instruction { AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + Context.EmitLdvec(Op.Rd); + Context.EmitStvectmp(); + int Elems = 8 >> Op.Size; int Part = Op.RegisterSize == ARegisterSize.SIMD128 ? Elems : 0; |