Misc cleanup (#708)

* Fix typos

* Remove unneeded using statements

* Enforce var style more

* Remove redundant qualifiers

* Fix some indentation

* Disable naming warnings on files with external enum names

* Fix build

* Mass find & replace for comments with no spacing

* Standardize todo capitalization and for/if spacing

6 files changed, 46 insertions, 46 deletions

diff --git a/ChocolArm64/Decoders/Condition.cs b/ChocolArm64/Decoders/Condition.cs
index 3f341a98..ef4b2959 100644
--- a/ChocolArm64/Decoders/Condition.cs
+++ b/ChocolArm64/Decoders/Condition.cs
@@ -24,8 +24,8 @@ namespace ChocolArm64.Decoders
     {
         public static Condition Invert(this Condition cond)
         {
-            //Bit 0 of all conditions is basically a negation bit, so
-            //inverting this bit has the effect of inverting the condition.
+            // Bit 0 of all conditions is basically a negation bit, so
+            // inverting this bit has the effect of inverting the condition.
             return (Condition)((int)cond ^ 1);
         }
     }
diff --git a/ChocolArm64/Decoders/Decoder.cs b/ChocolArm64/Decoders/Decoder.cs
index 6a95bc28..a1eeee15 100644
--- a/ChocolArm64/Decoders/Decoder.cs
+++ b/ChocolArm64/Decoders/Decoder.cs
@@ -29,12 +29,12 @@ namespace ChocolArm64.Decoders
 
             if (IsBranch(lastOp) && !IsCall(lastOp) && lastOp is IOpCodeBImm op)
             {
-                //It's possible that the branch on this block lands on the middle of the block.
-                //This is more common on tight loops. In this case, we can improve the codegen
-                //a bit by changing the CFG and either making the branch point to the same block
-                //(which indicates that the block is a loop that jumps back to the start), and the
-                //other possible case is a jump somewhere on the middle of the block, which is
-                //also a loop, but in this case we need to split the block in half.
+                // It's possible that the branch on this block lands on the middle of the block.
+                // This is more common on tight loops. In this case, we can improve the codegen
+                // a bit by changing the CFG and either making the branch point to the same block
+                // (which indicates that the block is a loop that jumps back to the start), and the
+                // other possible case is a jump somewhere on the middle of the block, which is
+                // also a loop, but in this case we need to split the block in half.
                 if ((ulong)op.Imm == address)
                 {
                     block.Branch = block;
@@ -79,7 +79,7 @@ namespace ChocolArm64.Decoders
 
             while (workQueue.TryDequeue(out Block currBlock))
             {
-                //Check if the current block is inside another block.
+                // Check if the current block is inside another block.
                 if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
                 {
                     Block nBlock = blocks[nBlkIndex];
@@ -96,7 +96,7 @@ namespace ChocolArm64.Decoders
                     continue;
                 }
 
-                //If we have a block after the current one, set the limit address.
+                // If we have a block after the current one, set the limit address.
                 ulong limitAddress = ulong.MaxValue;
 
                 if (nBlkIndex != blocks.Count)
@@ -119,10 +119,10 @@ namespace ChocolArm64.Decoders
 
                 if (currBlock.OpCodes.Count != 0)
                 {
-                    //Set child blocks. "Branch" is the block the branch instruction
-                    //points to (when taken), "Next" is the block at the next address,
-                    //executed when the branch is not taken. For Unconditional Branches
-                    //(except BL/BLR that are sub calls) or end of executable, Next is null.
+                    // Set child blocks. "Branch" is the block the branch instruction
+                    // points to (when taken), "Next" is the block at the next address,
+                    // executed when the branch is not taken. For Unconditional Branches
+                    // (except BL/BLR that are sub calls) or end of executable, Next is null.
                     OpCode64 lastOp = currBlock.GetLastOp();
 
                     bool isCall = IsCall(lastOp);
@@ -138,7 +138,7 @@ namespace ChocolArm64.Decoders
                     }
                 }
 
-                //Insert the new block on the list (sorted by address).
+                // Insert the new block on the list (sorted by address).
                 if (blocks.Count != 0)
                 {
                     Block nBlock = blocks[nBlkIndex];
@@ -236,25 +236,25 @@ namespace ChocolArm64.Decoders
                 return false;
             }
 
-            //Note: On ARM32, most instructions have conditional execution,
-            //so there's no "Always" (unconditional) branch like on ARM64.
-            //We need to check if the condition is "Always" instead.
+            // Note: On ARM32, most instructions have conditional execution,
+            // so there's no "Always" (unconditional) branch like on ARM64.
+            // We need to check if the condition is "Always" instead.
             return IsAarch32Branch(op) && op.Cond >= Condition.Al;
         }
 
         private static bool IsAarch32Branch(OpCode64 opCode)
         {
-            //Note: On ARM32, most ALU operations can write to R15 (PC),
-            //so we must consider such operations as a branch in potential aswell.
+            // Note: On ARM32, most ALU operations can write to R15 (PC),
+            // so we must consider such operations as a branch in potential as well.
             if (opCode is IOpCode32Alu opAlu && opAlu.Rd == RegisterAlias.Aarch32Pc)
             {
                 return true;
             }
 
-            //Same thing for memory operations. We have the cases where PC is a target
-            //register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
-            //a write back to PC (wback == true && Rn == 15), however the later may
-            //be "undefined" depending on the CPU, so compilers should not produce that.
+            // Same thing for memory operations. We have the cases where PC is a target
+            // register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
+            // a write back to PC (wback == true && Rn == 15), however the later may
+            // be "undefined" depending on the CPU, so compilers should not produce that.
             if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
             {
                 int rt, rn;
@@ -268,8 +268,8 @@ namespace ChocolArm64.Decoders
                     wBack  = opMem.WBack;
                     isLoad = opMem.IsLoad;
 
-                    //For the dual load, we also need to take into account the
-                    //case were Rt2 == 15 (PC).
+                    // For the dual load, we also need to take into account the
+                    // case were Rt2 == 15 (PC).
                     if (rt == 14 && opMem.Emitter == InstEmit32.Ldrd)
                     {
                         rt = RegisterAlias.Aarch32Pc;
@@ -296,14 +296,14 @@ namespace ChocolArm64.Decoders
                 }
             }
 
-            //Explicit branch instructions.
+            // Explicit branch instructions.
             return opCode is IOpCode32BImm ||
                    opCode is IOpCode32BReg;
         }
 
         private static bool IsCall(OpCode64 opCode)
         {
-            //TODO (CQ): ARM32 support.
+            // TODO (CQ): ARM32 support.
             return opCode.Emitter == InstEmit.Bl ||
                    opCode.Emitter == InstEmit.Blr;
         }
diff --git a/ChocolArm64/Decoders/OpCode32.cs b/ChocolArm64/Decoders/OpCode32.cs
index 8534b78f..1909757c 100644
--- a/ChocolArm64/Decoders/OpCode32.cs
+++ b/ChocolArm64/Decoders/OpCode32.cs
@@ -16,8 +16,8 @@ namespace ChocolArm64.Decoders
 
         public uint GetPc()
         {
-            //Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
-            //the PC actually points 2 instructions ahead.
+            // Due to backwards compatibility and legacy behavior of ARMv4 CPUs pipeline,
+            // the PC actually points 2 instructions ahead.
             return (uint)Position + (uint)OpCodeSizeInBytes * 2;
         }
     }
diff --git a/ChocolArm64/Decoders/OpCode32BImm.cs b/ChocolArm64/Decoders/OpCode32BImm.cs
index 43f191eb..7f3c29a6 100644
--- a/ChocolArm64/Decoders/OpCode32BImm.cs
+++ b/ChocolArm64/Decoders/OpCode32BImm.cs
@@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders
         {
             uint pc = GetPc();
 
-            //When the codition is never, the instruction is BLX to Thumb mode.
+            // When the condition is never, the instruction is BLX to Thumb mode.
             if (Cond != Condition.Nv)
             {
                 pc &= ~3u;
diff --git a/ChocolArm64/Decoders/OpCodeMemImm64.cs b/ChocolArm64/Decoders/OpCodeMemImm64.cs
index d9f322ea..01a62ef5 100644
--- a/ChocolArm64/Decoders/OpCodeMemImm64.cs
+++ b/ChocolArm64/Decoders/OpCodeMemImm64.cs
@@ -23,16 +23,16 @@ namespace ChocolArm64.Decoders
             Extend64 = ((opCode >> 22) & 3) == 2;
             WBack    = ((opCode >> 24) & 1) == 0;
 
-            //The type is not valid for the Unsigned Immediate 12-bits encoding,
-            //because the bits 11:10 are used for the larger Immediate offset.
+            // The type is not valid for the Unsigned Immediate 12-bits encoding,
+            // because the bits 11:10 are used for the larger Immediate offset.
             MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
 
             PostIdx  = type == MemOp.PostIndexed;
             Unscaled = type == MemOp.Unscaled ||
                        type == MemOp.Unprivileged;
 
-            //Unscaled and Unprivileged doesn't write back,
-            //but they do use the 9-bits Signed Immediate.
+            // Unscaled and Unprivileged doesn't write back,
+            // but they do use the 9-bits Signed Immediate.
             if (Unscaled)
             {
                 WBack = false;
@@ -40,12 +40,12 @@ namespace ChocolArm64.Decoders
 
             if (WBack || Unscaled)
             {
-                //9-bits Signed Immediate.
+                // 9-bits Signed Immediate.
                 Imm = (opCode << 11) >> 23;
             }
             else
             {
-                //12-bits Unsigned Immediate.
+                // 12-bits Unsigned Immediate.
                 Imm = ((opCode >> 10) & 0xfff) << Size;
             }
         }
diff --git a/ChocolArm64/Decoders/OpCodeSimdImm64.cs b/ChocolArm64/Decoders/OpCodeSimdImm64.cs
index 37ee504d..27f586f1 100644
--- a/ChocolArm64/Decoders/OpCodeSimdImm64.cs
+++ b/ChocolArm64/Decoders/OpCodeSimdImm64.cs
@@ -30,14 +30,14 @@ namespace ChocolArm64.Decoders
                 switch (op | (modeLow << 1))
                 {
                     case 0:
-                        //64-bits Immediate.
-                        //Transform abcd efgh into abcd efgh abcd efgh ...
+                        // 64-bits Immediate.
+                        // Transform abcd efgh into abcd efgh abcd efgh ...
                         imm = (long)((ulong)imm * 0x0101010101010101);
                         break;
 
                     case 1:
-                        //64-bits Immediate.
-                        //Transform abcd efgh into aaaa aaaa bbbb bbbb ...
+                        // 64-bits Immediate.
+                        // Transform abcd efgh into aaaa aaaa bbbb bbbb ...
                         imm = (imm & 0xf0) >> 4 | (imm & 0x0f) << 4;
                         imm = (imm & 0xcc) >> 2 | (imm & 0x33) << 2;
                         imm = (imm & 0xaa) >> 1 | (imm & 0x55) << 1;
@@ -52,29 +52,29 @@ namespace ChocolArm64.Decoders
 
                     case 2:
                     case 3:
-                        //Floating point Immediate.
+                        // Floating point Immediate.
                         imm = DecoderHelper.DecodeImm8Float(imm, Size);
                         break;
                 }
             }
             else if ((modeHigh & 0b110) == 0b100)
             {
-                //16-bits shifted Immediate.
+                // 16-bits shifted Immediate.
                 Size = 1; imm <<= (modeHigh & 1) << 3;
             }
             else if ((modeHigh & 0b100) == 0b000)
             {
-                //32-bits shifted Immediate.
+                // 32-bits shifted Immediate.
                 Size = 2; imm <<= modeHigh << 3;
             }
             else if ((modeHigh & 0b111) == 0b110)
             {
-                //32-bits shifted Immediate (fill with ones).
+                // 32-bits shifted Immediate (fill with ones).
                 Size = 2; imm = ShlOnes(imm, 8 << modeLow);
             }
             else
             {
-                //8 bits without shift.
+                // 8 bits without shift.
                 Size = 0;
             }