diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-12-02 01:34:43 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-12-01 22:34:43 -0200 |
| commit | ad00fd02442cf9c0f00c4562635738042b521efa (patch) | |
| tree | cf1e9607e41f616d2c0ad171406fc1d271d45456 /ChocolArm64/Decoders/OpCodeSimdFcond64.cs | |
| parent | 9b22e8af5ee3e0896fc5f464022579ef0713e504 (diff) | |
Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs
* Update InstEmitSimdShift.cs
* Update SoftFallback.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFallback.cs
* Update Optimizations.cs
* Update InstEmitSimdLogical.cs
* Update InstEmitSimdArithmetic.cs
Diffstat (limited to 'ChocolArm64/Decoders/OpCodeSimdFcond64.cs')
| -rw-r--r-- | ChocolArm64/Decoders/OpCodeSimdFcond64.cs | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs index b0f1c0eb..f805b3c1 100644 --- a/ChocolArm64/Decoders/OpCodeSimdFcond64.cs +++ b/ChocolArm64/Decoders/OpCodeSimdFcond64.cs @@ -10,8 +10,8 @@ namespace ChocolArm64.Decoders public OpCodeSimdFcond64(Inst inst, long position, int opCode) : base(inst, position, opCode) { - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Cond)((opCode >> 12) & 0xf); } } -}
\ No newline at end of file +} |