diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2019-01-29 13:06:11 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-29 13:06:11 -0300 |
| commit | c1bdf19061ec679aa3c69eda2a41337e3e809014 (patch) | |
| tree | f3813b8df8ff8dd1fbf73fd085893b0df21850dc /ChocolArm64/Decoders/OpCodeBRegT16.cs | |
| parent | 8f7fcede7fa98c605925dc7b9316940960543bf1 (diff) | |
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
Diffstat (limited to 'ChocolArm64/Decoders/OpCodeBRegT16.cs')
| -rw-r--r-- | ChocolArm64/Decoders/OpCodeBRegT16.cs | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/ChocolArm64/Decoders/OpCodeBRegT16.cs b/ChocolArm64/Decoders/OpCodeBRegT16.cs deleted file mode 100644 index c6c25130..00000000 --- a/ChocolArm64/Decoders/OpCodeBRegT16.cs +++ /dev/null @@ -1,14 +0,0 @@ -using ChocolArm64.Instructions; - -namespace ChocolArm64.Decoders -{ - class OpCodeBRegT16 : OpCodeT16, IOpCodeBReg32 - { - public int Rm { get; private set; } - - public OpCodeBRegT16(Inst inst, long position, int opCode) : base(inst, position, opCode) - { - Rm = (opCode >> 3) & 0xf; - } - } -}
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