diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2019-01-29 13:06:11 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-29 13:06:11 -0300 |
| commit | c1bdf19061ec679aa3c69eda2a41337e3e809014 (patch) | |
| tree | f3813b8df8ff8dd1fbf73fd085893b0df21850dc /ChocolArm64/Decoders/OpCode32MemImm8.cs | |
| parent | 8f7fcede7fa98c605925dc7b9316940960543bf1 (diff) | |
Implement some ARM32 memory instructions and CMP (#565)
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants)
* Rename some opcode classes and flag masks for consistency
* Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations
* Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC
* Re-align arm32 instructions on the opcode table
Diffstat (limited to 'ChocolArm64/Decoders/OpCode32MemImm8.cs')
| -rw-r--r-- | ChocolArm64/Decoders/OpCode32MemImm8.cs | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/ChocolArm64/Decoders/OpCode32MemImm8.cs b/ChocolArm64/Decoders/OpCode32MemImm8.cs new file mode 100644 index 00000000..02e446e8 --- /dev/null +++ b/ChocolArm64/Decoders/OpCode32MemImm8.cs @@ -0,0 +1,15 @@ +using ChocolArm64.Instructions; + +namespace ChocolArm64.Decoders +{ + class OpCode32MemImm8 : OpCode32Mem + { + public OpCode32MemImm8(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + int imm4L = (opCode >> 0) & 0xf; + int imm4H = (opCode >> 8) & 0xf; + + Imm = imm4L | (imm4H << 4); + } + } +}
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