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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-04-20 17:40:15 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-04-20 12:40:15 -0300 |
| commit | 2ccd995cb27d95d056f8b6f270cb74012bfb7a33 (patch) | |
| tree | 4c550626f7a352b0456edcaa22bf9d5d5bf87a9a /ChocolArm64/Decoder | |
| parent | 03002f6537e3208e6951bc9092e958985e200c7d (diff) | |
Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
Diffstat (limited to 'ChocolArm64/Decoder')
0 files changed, 0 insertions, 0 deletions