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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-04-12 16:52:00 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-04-12 11:52:00 -0300 |
| commit | 262b5b80541d23ed248d5b4f2220a479a35d5969 (patch) | |
| tree | 0ba1d4b453dcffe7c00b7354264e4ac4d91317dc /ChocolArm64/Decoder/AOpCodeSimdShImm.cs | |
| parent | 9227b0ea59c6f5f5233bbedf633dc68097275129 (diff) | |
Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)
* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdShImm.cs')
0 files changed, 0 insertions, 0 deletions