diff options
| author | Alex Barney <thealexbarney@gmail.com> | 2018-10-30 19:43:02 -0600 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-10-30 22:43:02 -0300 |
| commit | 9cb57fb4bb3bbae0ae052a5af4a96a49fc5d864d (patch) | |
| tree | 0c97425aeb311c142bc92a6fcc503cb2c07d4376 /ChocolArm64/Decoder/AOpCodeSimdMemMs.cs | |
| parent | 5a87e58183578f5b84ca8d01cbb76aed11820f78 (diff) | |
Adjust naming conventions for Ryujinx and ChocolArm64 projects (#484)
* Change naming convention for Ryujinx project
* Change naming convention for ChocolArm64 project
* Fix NaN
* Remove unneeded this. from Ryujinx project
* Adjust naming from new PRs
* Name changes based on feedback
* How did this get removed?
* Rebasing fix
* Change FP enum case
* Remove prefix from ChocolArm64 classes - Part 1
* Remove prefix from ChocolArm64 classes - Part 2
* Fix alignment from last commit's renaming
* Rename namespaces
* Rename stragglers
* Fix alignment
* Rename OpCode class
* Missed a few
* Adjust alignment
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdMemMs.cs')
| -rw-r--r-- | ChocolArm64/Decoder/AOpCodeSimdMemMs.cs | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemMs.cs b/ChocolArm64/Decoder/AOpCodeSimdMemMs.cs deleted file mode 100644 index a54e2360..00000000 --- a/ChocolArm64/Decoder/AOpCodeSimdMemMs.cs +++ /dev/null @@ -1,49 +0,0 @@ -using ChocolArm64.Instruction; -using ChocolArm64.State; - -namespace ChocolArm64.Decoder -{ - class AOpCodeSimdMemMs : AOpCodeMemReg, IAOpCodeSimd - { - public int Reps { get; private set; } - public int SElems { get; private set; } - public int Elems { get; private set; } - public bool WBack { get; private set; } - - public AOpCodeSimdMemMs(AInst Inst, long Position, int OpCode) : base(Inst, Position, OpCode) - { - switch ((OpCode >> 12) & 0xf) - { - case 0b0000: Reps = 1; SElems = 4; break; - case 0b0010: Reps = 4; SElems = 1; break; - case 0b0100: Reps = 1; SElems = 3; break; - case 0b0110: Reps = 3; SElems = 1; break; - case 0b0111: Reps = 1; SElems = 1; break; - case 0b1000: Reps = 1; SElems = 2; break; - case 0b1010: Reps = 2; SElems = 1; break; - - default: Inst = AInst.Undefined; return; - } - - Size = (OpCode >> 10) & 3; - WBack = ((OpCode >> 23) & 1) != 0; - - bool Q = ((OpCode >> 30) & 1) != 0; - - if (!Q && Size == 3 && SElems != 1) - { - Inst = AInst.Undefined; - - return; - } - - Extend64 = false; - - RegisterSize = Q - ? ARegisterSize.SIMD128 - : ARegisterSize.SIMD64; - - Elems = (GetBitsCount() >> 3) >> Size; - } - } -}
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