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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-10-14 04:35:16 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-10-13 23:35:16 -0300 |
| commit | 894459fcd7797b1e38f2448797d83856d11b6e23 (patch) | |
| tree | 87a67e3b80cba4b05a29d243db63d130e1b362c2 /ChocolArm64/Decoder/AOpCodeSimdImm.cs | |
| parent | ac1a379265d0c02a8bd4a146c205f21e2d00f3ab (diff) | |
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update ASoftFloat.cs
* Update AOpCodeSimdRegElemF.cs
* Update CpuTestSimdIns.cs
* Update CpuTestSimdRegElem.cs
* Create CpuTestSimdRegElemF.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Superseded Fmul_Se Test. Nit.
* Address PR feedback.
* Address PR feedback.
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update AInstEmitSimdShift.cs
Diffstat (limited to 'ChocolArm64/Decoder/AOpCodeSimdImm.cs')
0 files changed, 0 insertions, 0 deletions