Add a new JIT compiler for CPU code (#693)

* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary

1 files changed, 130 insertions, 0 deletions

diff --git a/ARMeilleure/State/ExecutionContext.cs b/ARMeilleure/State/ExecutionContext.cs
new file mode 100644
index 00000000..22cfcb69
--- /dev/null
+++ b/ARMeilleure/State/ExecutionContext.cs
@@ -0,0 +1,130 @@
+using System;
+using System.Diagnostics;
+
+namespace ARMeilleure.State
+{
+    public class ExecutionContext : IExecutionContext
+    {
+        private const int MinCountForCheck = 40000;
+
+        private NativeContext _nativeContext;
+
+        internal IntPtr NativeContextPtr => _nativeContext.BasePtr;
+
+        private bool _interrupted;
+
+        private static Stopwatch _tickCounter;
+
+        private static double _hostTickFreq;
+
+        public uint CtrEl0   => 0x8444c004;
+        public uint DczidEl0 => 0x00000004;
+
+        public ulong CntfrqEl0 { get; set; }
+        public ulong CntpctEl0
+        {
+            get
+            {
+                double ticks = _tickCounter.ElapsedTicks * _hostTickFreq;
+
+                return (ulong)(ticks * CntfrqEl0);
+            }
+        }
+
+        public long TpidrEl0 { get; set; }
+        public long Tpidr    { get; set; }
+
+        public FPCR Fpcr { get; set; }
+        public FPSR Fpsr { get; set; }
+
+        public bool IsAarch32 { get; set; }
+
+        internal ExecutionMode ExecutionMode
+        {
+            get
+            {
+                if (IsAarch32)
+                {
+                    return GetPstateFlag(PState.TFlag)
+                        ? ExecutionMode.Aarch32Thumb
+                        : ExecutionMode.Aarch32Arm;
+                }
+                else
+                {
+                    return ExecutionMode.Aarch64;
+                }
+            }
+        }
+
+        public bool Running { get; set; }
+
+        public event EventHandler<EventArgs>              Interrupt;
+        public event EventHandler<InstExceptionEventArgs> Break;
+        public event EventHandler<InstExceptionEventArgs> SupervisorCall;
+        public event EventHandler<InstUndefinedEventArgs> Undefined;
+
+        static ExecutionContext()
+        {
+            _hostTickFreq = 1.0 / Stopwatch.Frequency;
+
+            _tickCounter = new Stopwatch();
+
+            _tickCounter.Start();
+        }
+
+        public ExecutionContext()
+        {
+            _nativeContext = new NativeContext();
+
+            Running = true;
+
+            _nativeContext.SetCounter(MinCountForCheck);
+        }
+
+        public ulong GetX(int index)              => _nativeContext.GetX(index);
+        public void  SetX(int index, ulong value) => _nativeContext.SetX(index, value);
+
+        public V128 GetV(int index)             => _nativeContext.GetV(index);
+        public void SetV(int index, V128 value) => _nativeContext.SetV(index, value);
+
+        public bool GetPstateFlag(PState flag)             => _nativeContext.GetPstateFlag(flag);
+        public void SetPstateFlag(PState flag, bool value) => _nativeContext.SetPstateFlag(flag, value);
+
+        internal void CheckInterrupt()
+        {
+            if (_interrupted)
+            {
+                _interrupted = false;
+
+                Interrupt?.Invoke(this, EventArgs.Empty);
+            }
+
+            _nativeContext.SetCounter(MinCountForCheck);
+        }
+
+        public void RequestInterrupt()
+        {
+            _interrupted = true;
+        }
+
+        internal void OnBreak(ulong address, int imm)
+        {
+            Break?.Invoke(this, new InstExceptionEventArgs(address, imm));
+        }
+
+        internal void OnSupervisorCall(ulong address, int imm)
+        {
+            SupervisorCall?.Invoke(this, new InstExceptionEventArgs(address, imm));
+        }
+
+        internal void OnUndefined(ulong address, int opCode)
+        {
+            Undefined?.Invoke(this, new InstUndefinedEventArgs(address, opCode));
+        }
+
+        public void Dispose()
+        {
+            _nativeContext.Dispose();
+        }
+    }
+}
\ No newline at end of file