diff options
| author | sharmander <saldabain.dev@gmail.com> | 2020-12-14 22:01:52 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-15 00:01:52 -0300 |
| commit | 3332b29f01993d22195f417d39ae4074d53fb55c (patch) | |
| tree | f573fb1e8113fd3359d97e99b7d9cdebef4265af /ARMeilleure/Instructions | |
| parent | 47ba81c661c7ccd8bf2c972b73ad444cbf0d9744 (diff) | |
CPU: Implement VFMA (Vector) (#1762)
* Implement VFMA.F64
* Simplify switch
* Simplify FMA Instructions into their own IntrinsicType.
* Remove whitespace
* Fix indentation
* Change tests for Vfnms -- disable inf / nan
* Move args up, not description ;)
* Implementation Complete.
All Tests Pass (Slow / Fast Path)
* Move location of function in assembler + test updates.
* Shift params upwards
* Remove unused function
* Update PTC version.
* Add comments / re-oreder opcode table.
* Remove whitespace
* Fix nit
* Fix nit.
* Fix whitespace
* Wrong opcode was used by a bad merge.
* Addressed rip's comments.
Diffstat (limited to 'ARMeilleure/Instructions')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | 17 | ||||
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdHelper32.cs | 12 |
2 files changed, 29 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index d72df97c..40289520 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -252,6 +252,23 @@ namespace ARMeilleure.Instructions } } + public static void Vfma_V(ArmEmitterContext context) // Fused. + { + if (Optimizations.FastFP && Optimizations.UseFma) + { + // Vectors contain elements that are 32-bits in length always. The only thing that will change is the number of elements in a vector. + // The 64-bit variant will never be used. + EmitVectorTernaryOpF32(context, Intrinsic.X86Vfmadd231ps, Intrinsic.X86Vfmadd231pd); + } + else + { + EmitVectorTernaryOpF32(context, (op1, op2, op3) => + { + return EmitSoftFloatCall(context, nameof(SoftFloat32.FPMulAdd), op1, op2, op3); + }); + } + } + public static void Vfma_S(ArmEmitterContext context) // Fused. { if (Optimizations.FastFP && Optimizations.UseSse2) diff --git a/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/ARMeilleure/Instructions/InstEmitSimdHelper32.cs index 75aa7220..2d5d4ba9 100644 --- a/ARMeilleure/Instructions/InstEmitSimdHelper32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdHelper32.cs @@ -820,6 +820,18 @@ namespace ARMeilleure.Instructions }); } + public static void EmitVectorTernaryOpF32(ArmEmitterContext context, Intrinsic inst32, Intrinsic inst64) + { + OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp; + + Intrinsic inst = (op.Size & 1) != 0 ? inst64 : inst32; + + EmitVectorTernaryOpSimd32(context, (d, n, m) => + { + return context.AddIntrinsic(inst, d, n, m); + }); + } + public static void EmitScalarUnaryOpSimd32(ArmEmitterContext context, Func1I scalarFunc) { OpCode32SimdS op = (OpCode32SimdS)context.CurrOp; |