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authorgdkchan <gab.dark.100@gmail.com>2020-03-10 02:17:30 -0300
committerGitHub <noreply@github.com>2020-03-10 16:17:30 +1100
commit89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (patch)
tree3f487a86d3495feefd904d4cd7195d9c798c008b /ARMeilleure/Instructions/InstEmitSimdMove32.cs
parent08c0e3829bc96932d386de18647bde2768fe26ed (diff)
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions * Rename <dt> to <size> on test description * Rename Widen to Long and improve VMOVL implementation a bit
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitSimdMove32.cs')
-rw-r--r--ARMeilleure/Instructions/InstEmitSimdMove32.cs30
1 files changed, 30 insertions, 0 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/ARMeilleure/Instructions/InstEmitSimdMove32.cs
index 17ff66b0..f11f9cc5 100644
--- a/ARMeilleure/Instructions/InstEmitSimdMove32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdMove32.cs
@@ -139,6 +139,36 @@ namespace ARMeilleure.Instructions
}
}
+ public static void Vmovl(ArmEmitterContext context)
+ {
+ OpCode32SimdLong op = (OpCode32SimdLong)context.CurrOp;
+
+ Operand res = context.VectorZero();
+
+ int elems = op.GetBytesCount() >> op.Size;
+
+ for (int index = 0; index < elems; index++)
+ {
+ Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
+
+ if (op.Size == 2)
+ {
+ if (op.U)
+ {
+ me = context.ZeroExtend32(OperandType.I64, me);
+ }
+ else
+ {
+ me = context.SignExtend32(OperandType.I64, me);
+ }
+ }
+
+ res = EmitVectorInsert(context, res, me, index, op.Size + 1);
+ }
+
+ context.Copy(GetVecA32(op.Qd), res);
+ }
+
public static void Vtbl(ArmEmitterContext context)
{
OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;