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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-08-13 07:34:02 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-13 02:34:02 -0300 |
| commit | 6938988427e7f96adcd8fe76fe5d0a19b014b2b2 (patch) | |
| tree | 39b049344e5d00b5f152b5354e7c8090ebf46c41 /ARMeilleure/Instructions/InstEmitSimdHelper32.cs | |
| parent | 1ad9045c6b00a5c729c8c7d697f3da54ed177883 (diff) | |
Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
* Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests.
* Address PR feedback & Nit.
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitSimdHelper32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdHelper32.cs | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdHelper32.cs b/ARMeilleure/Instructions/InstEmitSimdHelper32.cs index e045c601..a962c0fc 100644 --- a/ARMeilleure/Instructions/InstEmitSimdHelper32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdHelper32.cs @@ -906,7 +906,7 @@ namespace ARMeilleure.Instructions OpCode32SimdRegS op = (OpCode32SimdRegS)context.CurrOp; bool doubleSize = (op.Size & 1) != 0; - int shift = doubleSize ? 1 : 2; + Intrinsic inst1 = doubleSize ? inst64pt1 : inst32pt1; Intrinsic inst2 = doubleSize ? inst64pt2 : inst32pt2; |