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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-07-17 15:57:49 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-17 10:57:49 -0300 |
| commit | 56a61a57582e0fa7951bdb3d96b343ac01063e1f (patch) | |
| tree | f10bb972dc0dc71e101220e4570c6b682b91b8a6 /ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | |
| parent | 20774dab14ca8362e716ce87f975be7ea77beead (diff) | |
CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)
* Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests.
* Update Ptc.cs
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs index cc6e6edb..f7f3d47e 100644 --- a/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs @@ -33,7 +33,7 @@ namespace ARMeilleure.Instructions public static void Vabs_V(ArmEmitterContext context) { - OpCode32Simd op = (OpCode32Simd)context.CurrOp; + OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp; if (op.F) { @@ -385,22 +385,22 @@ namespace ARMeilleure.Instructions public static void Vneg_V(ArmEmitterContext context) { - OpCode32Simd op = (OpCode32Simd)context.CurrOp; + OpCode32SimdCmpZ op = (OpCode32SimdCmpZ)context.CurrOp; if (op.F) { - if (Optimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { EmitVectorUnaryOpSimd32(context, (m) => { if ((op.Size & 1) == 0) { - Operand mask = X86GetScalar(context, -0f); + Operand mask = X86GetAllElements(context, -0f); return context.AddIntrinsic(Intrinsic.X86Xorps, mask, m); } else { - Operand mask = X86GetScalar(context, -0d); + Operand mask = X86GetAllElements(context, -0d); return context.AddIntrinsic(Intrinsic.X86Xorpd, mask, m); } }); |