diff options
| author | merry <git@mary.rs> | 2022-02-17 22:39:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-17 19:39:45 -0300 |
| commit | 98e05ee4b7aa8a08088b1f0cd6c581bb50f11395 (patch) | |
| tree | af9cf98afb6c44161fadd87bfe7946c7a4250e47 /ARMeilleure/Instructions/InstEmitMemory32.cs | |
| parent | 868919e101ba5d5ad1cfccb5017b294fec11c6e3 (diff) | |
ARMeilleure: Thumb support (All T16 instructions) (#3105)
* Decoders: Add InITBlock argument
* OpCodeTable: Minor cleanup
* OpCodeTable: Remove existing thumb instruction implementations
* OpCodeTable: Prepare for thumb instructions
* OpCodeTables: Improve thumb fast lookup
* Tests: Prepare for thumb tests
* T16: Implement BX
* T16: Implement LSL/LSR/ASR (imm)
* T16: Implement ADDS, SUBS (reg)
* T16: Implement ADDS, SUBS (3-bit immediate)
* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)
* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
* T16: Implement ADD, CMP, MOV (high reg)
* T16: Implement BLX (reg)
* T16: Implement LDR (literal)
* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)
* T16: Implement {LDR,STR}{,B,H} (immediate)
* T16: Implement LDR/STR (SP)
* T16: Implement ADR
* T16: Implement Add to SP (immediate)
* T16: Implement ADD/SUB (SP)
* T16: Implement SXTH, SXTB, UXTH, UTXB
* T16: Implement CBZ, CBNZ
* T16: Implement PUSH, POP
* T16: Implement REV, REV16, REVSH
* T16: Implement NOP
* T16: Implement LDM, STM
* T16: Implement SVC
* T16: Implement B (conditional)
* T16: Implement B (unconditional)
* T16: Implement IT
* fixup! T16: Implement ADD/SUB (SP)
* fixup! T16: Implement Add to SP (immediate)
* fixup! T16: Implement IT
* CpuTestThumb: Add randomized tests
* Remove inITBlock argument
* Address nits
* Use index to handle IfThenBlockState
* Reduce line noise
* fixup
* nit
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitMemory32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitMemory32.cs | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/ARMeilleure/Instructions/InstEmitMemory32.cs b/ARMeilleure/Instructions/InstEmitMemory32.cs index af9eaf1a..e15f6a5b 100644 --- a/ARMeilleure/Instructions/InstEmitMemory32.cs +++ b/ARMeilleure/Instructions/InstEmitMemory32.cs @@ -32,7 +32,7 @@ namespace ARMeilleure.Instructions public static void Ldm(ArmEmitterContext context) { - OpCode32MemMult op = (OpCode32MemMult)context.CurrOp; + IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp; Operand n = GetIntA32(context, op.Rn); @@ -95,7 +95,7 @@ namespace ARMeilleure.Instructions public static void Stm(ArmEmitterContext context) { - OpCode32MemMult op = (OpCode32MemMult)context.CurrOp; + IOpCode32MemMult op = (IOpCode32MemMult)context.CurrOp; Operand n = context.Copy(GetIntA32(context, op.Rn)); @@ -151,7 +151,7 @@ namespace ARMeilleure.Instructions private static void EmitLoadOrStore(ArmEmitterContext context, int size, AccessType accType) { - OpCode32Mem op = (OpCode32Mem)context.CurrOp; + IOpCode32Mem op = (IOpCode32Mem)context.CurrOp; Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn)); Operand m = GetMemM(context, setCarry: false); @@ -255,5 +255,11 @@ namespace ARMeilleure.Instructions } } } + + public static void Adr(ArmEmitterContext context) + { + IOpCode32Adr op = (IOpCode32Adr)context.CurrOp; + SetIntA32(context, op.Rd, Const(op.Immediate)); + } } }
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