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authorTSR Berry <20988865+TSRBerry@users.noreply.github.com>2023-04-08 01:22:00 +0200
committerMary <thog@protonmail.com>2023-04-27 23:51:14 +0200
commitcee712105850ac3385cd0091a923438167433f9f (patch)
tree4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
parentcd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff)
Move solution and projects to src
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeT16AddSubSp.cs')
-rw-r--r--ARMeilleure/Decoders/OpCodeT16AddSubSp.cs23
1 files changed, 0 insertions, 23 deletions
diff --git a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs b/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
deleted file mode 100644
index b66fe0cd..00000000
--- a/ARMeilleure/Decoders/OpCodeT16AddSubSp.cs
+++ /dev/null
@@ -1,23 +0,0 @@
-using ARMeilleure.State;
-
-namespace ARMeilleure.Decoders
-{
- class OpCodeT16AddSubSp : OpCodeT16, IOpCode32AluImm
- {
- public int Rd => RegisterAlias.Aarch32Sp;
- public int Rn => RegisterAlias.Aarch32Sp;
-
- public bool? SetFlags => false;
-
- public int Immediate { get; }
-
- public bool IsRotated => false;
-
- public static new OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT16AddSubSp(inst, address, opCode);
-
- public OpCodeT16AddSubSp(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
- {
- Immediate = ((opCode >> 0) & 0x7f) << 2;
- }
- }
-}