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| author | gdkchan <gab.dark.100@gmail.com> | 2020-09-01 17:02:23 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-09-01 17:02:23 -0300 |
| commit | 6cc187da594a620f89df38ff537511138b03c9dc (patch) | |
| tree | 4b34d6ea95d4bef76eaa92e735a523ae90fe7bcc /ARMeilleure/Decoders/OpCodeSimdMemReg.cs | |
| parent | 3d294a9a6ccf5c620e328bfd87a8cf354b6af227 (diff) | |
SIMD&FP load/store with scale > 4 should be undefined (#1522)
* SIMD&FP load/store with scale > 4 should be undefined
* Catch more invalid encodings for FP&SIMD LDR/STR (reg variant)
* Set PTC version to PR number
Diffstat (limited to 'ARMeilleure/Decoders/OpCodeSimdMemReg.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCodeSimdMemReg.cs | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs index 7b783d63..cad8ca63 100644 --- a/ARMeilleure/Decoders/OpCodeSimdMemReg.cs +++ b/ARMeilleure/Decoders/OpCodeSimdMemReg.cs @@ -6,6 +6,13 @@ namespace ARMeilleure.Decoders { Size |= (opCode >> 21) & 4; + if (Size > 4) + { + Instruction = InstDescriptor.Undefined; + + return; + } + Extend64 = false; } } |
