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authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2020-08-13 07:34:02 +0200
committerGitHub <noreply@github.com>2020-08-13 02:34:02 -0300
commit6938988427e7f96adcd8fe76fe5d0a19b014b2b2 (patch)
tree39b049344e5d00b5f152b5354e7c8090ebf46c41 /ARMeilleure/Decoders/OpCode32SimdS.cs
parent1ad9045c6b00a5c729c8c7d697f3da54ed177883 (diff)
Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)
* Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. * Address PR feedback & Nit.
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdS.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdS.cs9
1 files changed, 6 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdS.cs b/ARMeilleure/Decoders/OpCode32SimdS.cs
index 2e860d9c..766cf4ba 100644
--- a/ARMeilleure/Decoders/OpCode32SimdS.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdS.cs
@@ -2,14 +2,17 @@
{
class OpCode32SimdS : OpCode32, IOpCode32Simd
{
- public int Vd { get; private set; }
- public int Vm { get; private set; }
- public int Opc { get; protected set; }
+ public int Vd { get; protected set; }
+ public int Vm { get; protected set; }
+ public int Opc { get; protected set; } // "with_zero" (Opc<1>) [Vcmp, Vcmpe].
+ public int Opc2 { get; private set; } // opc2 or RM (opc2<1:0>) [Vcvt, Vrint].
public int Size { get; protected set; }
public OpCode32SimdS(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Opc = (opCode >> 15) & 0x3;
+ Opc2 = (opCode >> 16) & 0x7;
+
Size = (opCode >> 8) & 0x3;
bool single = Size != 3;