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authorTSR Berry <20988865+TSRBerry@users.noreply.github.com>2023-04-08 01:22:00 +0200
committerMary <thog@protonmail.com>2023-04-27 23:51:14 +0200
commitcee712105850ac3385cd0091a923438167433f9f (patch)
tree4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /ARMeilleure/Decoders/OpCode32SimdRev.cs
parentcd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff)
Move solution and projects to src
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRev.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdRev.cs23
1 files changed, 0 insertions, 23 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRev.cs b/ARMeilleure/Decoders/OpCode32SimdRev.cs
deleted file mode 100644
index cb64765f..00000000
--- a/ARMeilleure/Decoders/OpCode32SimdRev.cs
+++ /dev/null
@@ -1,23 +0,0 @@
-namespace ARMeilleure.Decoders
-{
- class OpCode32SimdRev : OpCode32SimdCmpZ
- {
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, false);
- public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRev(inst, address, opCode, true);
-
- public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
- {
- if (Opc + Size >= 3)
- {
- Instruction = InstDescriptor.Undefined;
- return;
- }
-
- // Currently, this instruction is treated as though it's OPCODE is the true size,
- // which lets us deal with reversing vectors on a single element basis (eg. math magic an I64 rather than insert lots of I8s).
- int tempSize = Size;
- Size = 3 - Opc; // Op 0 is 64 bit, 1 is 32 and so on.
- Opc = tempSize;
- }
- }
-}