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| author | TSR Berry <20988865+TSRBerry@users.noreply.github.com> | 2023-04-08 01:22:00 +0200 |
|---|---|---|
| committer | Mary <thog@protonmail.com> | 2023-04-27 23:51:14 +0200 |
| commit | cee712105850ac3385cd0091a923438167433f9f (patch) | |
| tree | 4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs | |
| parent | cd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff) | |
Move solution and projects to src
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs b/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs deleted file mode 100644 index b87ac413..00000000 --- a/ARMeilleure/Decoders/OpCode32SimdRegElemLong.cs +++ /dev/null @@ -1,22 +0,0 @@ -namespace ARMeilleure.Decoders -{ - class OpCode32SimdRegElemLong : OpCode32SimdRegElem - { - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, false); - public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElemLong(inst, address, opCode, true); - - public OpCode32SimdRegElemLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) - { - Q = false; - F = false; - - RegisterSize = RegisterSize.Simd64; - - // (Vd & 1) != 0 || Size == 3 are also invalid, but they are checked on encoding. - if (Size == 0) - { - Instruction = InstDescriptor.Undefined; - } - } - } -} |
