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authorTSR Berry <20988865+TSRBerry@users.noreply.github.com>2023-04-08 01:22:00 +0200
committerMary <thog@protonmail.com>2023-04-27 23:51:14 +0200
commitcee712105850ac3385cd0091a923438167433f9f (patch)
tree4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /ARMeilleure/Decoders/OpCode32SimdRegElem.cs
parentcd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff)
Move solution and projects to src
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdRegElem.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdRegElem.cs31
1 files changed, 0 insertions, 31 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs b/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
deleted file mode 100644
index 173c5265..00000000
--- a/ARMeilleure/Decoders/OpCode32SimdRegElem.cs
+++ /dev/null
@@ -1,31 +0,0 @@
-namespace ARMeilleure.Decoders
-{
- class OpCode32SimdRegElem : OpCode32SimdReg
- {
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, false);
- public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdRegElem(inst, address, opCode, true);
-
- public OpCode32SimdRegElem(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
- {
- Q = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
- F = ((opCode >> 8) & 0x1) != 0;
- Size = (opCode >> 20) & 0x3;
-
- RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;
-
- if (Size == 1)
- {
- Vm = ((opCode >> 3) & 0x1) | ((opCode >> 4) & 0x2) | ((opCode << 2) & 0x1c);
- }
- else /* if (Size == 2) */
- {
- Vm = ((opCode >> 5) & 0x1) | ((opCode << 1) & 0x1e);
- }
-
- if (GetType() == typeof(OpCode32SimdRegElem) && DecoderHelper.VectorArgumentsInvalid(Q, Vd, Vn) || Size == 0 || (Size == 1 && F))
- {
- Instruction = InstDescriptor.Undefined;
- }
- }
- }
-}