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authormerry <git@mary.rs>2022-09-13 22:25:37 +0100
committerGitHub <noreply@github.com>2022-09-13 18:25:37 -0300
commite05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch)
tree87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32SimdImm.cs
parent66f16f43921bdd6d0f706d09aa37166d374dec2e (diff)
T32: Implement Asimd instructions (#3692)
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdImm.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdImm.cs7
1 files changed, 4 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdImm.cs b/ARMeilleure/Decoders/OpCode32SimdImm.cs
index 678f3064..bf0ca527 100644
--- a/ARMeilleure/Decoders/OpCode32SimdImm.cs
+++ b/ARMeilleure/Decoders/OpCode32SimdImm.cs
@@ -6,9 +6,10 @@
public long Immediate { get; }
public int Elems => GetBytesCount() >> Size;
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode);
+ public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, false);
+ public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdImm(inst, address, opCode, true);
- public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
+ public OpCode32SimdImm(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
{
Vd = (opCode >> 12) & 0xf;
Vd |= (opCode >> 18) & 0x10;
@@ -22,7 +23,7 @@
imm = ((uint)opCode >> 0) & 0xf;
imm |= ((uint)opCode >> 12) & 0x70;
- imm |= ((uint)opCode >> 17) & 0x80;
+ imm |= ((uint)opCode >> (isThumb ? 21 : 17)) & 0x80;
(Immediate, Size) = OpCodeSimdHelper.GetSimdImmediateAndSize(cMode, op, imm);