diff options
| author | merry <git@mary.rs> | 2022-09-13 22:25:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-13 18:25:37 -0300 |
| commit | e05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch) | |
| tree | 87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32Simd.cs | |
| parent | 66f16f43921bdd6d0f706d09aa37166d374dec2e (diff) | |
T32: Implement Asimd instructions (#3692)
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32Simd.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32Simd.cs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/ARMeilleure/Decoders/OpCode32Simd.cs b/ARMeilleure/Decoders/OpCode32Simd.cs index 51f39056..636aa0a8 100644 --- a/ARMeilleure/Decoders/OpCode32Simd.cs +++ b/ARMeilleure/Decoders/OpCode32Simd.cs @@ -7,14 +7,15 @@ public bool F { get; protected set; } public bool U { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, false); + public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32Simd(inst, address, opCode, true); - public OpCode32Simd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + public OpCode32Simd(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { Size = (opCode >> 20) & 0x3; Q = ((opCode >> 6) & 0x1) != 0; F = ((opCode >> 10) & 0x1) != 0; - U = ((opCode >> 24) & 0x1) != 0; + U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0; Opc = (opCode >> 7) & 0x3; RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64; |