aboutsummaryrefslogtreecommitdiff
path: root/ARMeilleure/CodeGen
diff options
context:
space:
mode:
authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2019-12-30 02:22:47 +0100
committergdkchan <gab.dark.100@gmail.com>2019-12-29 22:22:47 -0300
commit0915731a9dfc4e2b9263d4b30c2876446ff2d9b3 (patch)
tree46dd5369be3a2c2a3b8b6021ce164549de2b25e2 /ARMeilleure/CodeGen
parentad84f3a7b3b409ceab920f480dadcfe6eda62c92 (diff)
Implemented fast paths for: (#846)
* opt * Nit. * opt_p2 * Nit.
Diffstat (limited to 'ARMeilleure/CodeGen')
-rw-r--r--ARMeilleure/CodeGen/X86/Assembler.cs11
-rw-r--r--ARMeilleure/CodeGen/X86/CodeGenerator.cs28
-rw-r--r--ARMeilleure/CodeGen/X86/IntrinsicTable.cs3
-rw-r--r--ARMeilleure/CodeGen/X86/IntrinsicType.cs1
-rw-r--r--ARMeilleure/CodeGen/X86/X86Instruction.cs1
5 files changed, 40 insertions, 4 deletions
diff --git a/ARMeilleure/CodeGen/X86/Assembler.cs b/ARMeilleure/CodeGen/X86/Assembler.cs
index 24a122c3..4568253a 100644
--- a/ARMeilleure/CodeGen/X86/Assembler.cs
+++ b/ARMeilleure/CodeGen/X86/Assembler.cs
@@ -103,6 +103,7 @@ namespace ARMeilleure.CodeGen.X86
Add(X86Instruction.Cvtsi2sd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f2a, InstructionFlags.Vex | InstructionFlags.PrefixF2));
Add(X86Instruction.Cvtsi2ss, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f2a, InstructionFlags.Vex | InstructionFlags.PrefixF3));
Add(X86Instruction.Cvtss2sd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5a, InstructionFlags.Vex | InstructionFlags.PrefixF3));
+ Add(X86Instruction.Cvtss2si, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f2d, InstructionFlags.Vex | InstructionFlags.PrefixF3));
Add(X86Instruction.Div, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x060000f7, InstructionFlags.None));
Add(X86Instruction.Divpd, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex | InstructionFlags.Prefix66));
Add(X86Instruction.Divps, new InstructionInfo(BadOp, BadOp, BadOp, BadOp, 0x00000f5e, InstructionFlags.Vex));
@@ -791,6 +792,16 @@ namespace ARMeilleure.CodeGen.X86
}
}
+ public void WriteInstruction(
+ X86Instruction inst,
+ Operand dest,
+ Operand src1,
+ Operand src2,
+ OperandType type)
+ {
+ WriteInstruction(dest, src1, src2, inst, type);
+ }
+
public void WriteInstruction(X86Instruction inst, Operand dest, Operand source, byte imm)
{
WriteInstruction(dest, null, source, inst);
diff --git a/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/ARMeilleure/CodeGen/X86/CodeGenerator.cs
index d1224363..0268665c 100644
--- a/ARMeilleure/CodeGen/X86/CodeGenerator.cs
+++ b/ARMeilleure/CodeGen/X86/CodeGenerator.cs
@@ -269,11 +269,11 @@ namespace ARMeilleure.CodeGen.X86
{
if (dest.Type == OperandType.I32)
{
- context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32
+ context.Assembler.Movd(dest, source); // int _mm_cvtsi128_si32(__m128i a)
}
else /* if (dest.Type == OperandType.I64) */
{
- context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64
+ context.Assembler.Movq(dest, source); // __int64 _mm_cvtsi128_si64(__m128i a)
}
}
else
@@ -305,6 +305,26 @@ namespace ARMeilleure.CodeGen.X86
break;
}
+ case IntrinsicType.BinaryGpr:
+ {
+ Operand dest = operation.Destination;
+ Operand src1 = operation.GetSource(0);
+ Operand src2 = operation.GetSource(1);
+
+ EnsureSameType(dest, src1);
+
+ if (!HardwareCapabilities.SupportsVexEncoding)
+ {
+ EnsureSameReg(dest, src1);
+ }
+
+ Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger());
+
+ context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type);
+
+ break;
+ }
+
case IntrinsicType.BinaryImm:
{
Operand dest = operation.Destination;
@@ -1070,11 +1090,11 @@ namespace ARMeilleure.CodeGen.X86
if (source.Type == OperandType.I32)
{
- context.Assembler.Movd(dest, source);
+ context.Assembler.Movd(dest, source); // (__m128i _mm_cvtsi32_si128(int a))
}
else /* if (source.Type == OperandType.I64) */
{
- context.Assembler.Movq(dest, source);
+ context.Assembler.Movq(dest, source); // (__m128i _mm_cvtsi64_si128(__int64 a))
}
}
diff --git a/ARMeilleure/CodeGen/X86/IntrinsicTable.cs b/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
index e87de035..fd3b691d 100644
--- a/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
+++ b/ARMeilleure/CodeGen/X86/IntrinsicTable.cs
@@ -41,8 +41,11 @@ namespace ARMeilleure.CodeGen.X86
Add(Intrinsic.X86Cvtps2pd, new IntrinsicInfo(X86Instruction.Cvtps2pd, IntrinsicType.Unary));
Add(Intrinsic.X86Cvtsd2si, new IntrinsicInfo(X86Instruction.Cvtsd2si, IntrinsicType.UnaryToGpr));
Add(Intrinsic.X86Cvtsd2ss, new IntrinsicInfo(X86Instruction.Cvtsd2ss, IntrinsicType.Binary));
+ Add(Intrinsic.X86Cvtsi2sd, new IntrinsicInfo(X86Instruction.Cvtsi2sd, IntrinsicType.BinaryGpr));
Add(Intrinsic.X86Cvtsi2si, new IntrinsicInfo(X86Instruction.Movd, IntrinsicType.UnaryToGpr));
+ Add(Intrinsic.X86Cvtsi2ss, new IntrinsicInfo(X86Instruction.Cvtsi2ss, IntrinsicType.BinaryGpr));
Add(Intrinsic.X86Cvtss2sd, new IntrinsicInfo(X86Instruction.Cvtss2sd, IntrinsicType.Binary));
+ Add(Intrinsic.X86Cvtss2si, new IntrinsicInfo(X86Instruction.Cvtss2si, IntrinsicType.UnaryToGpr));
Add(Intrinsic.X86Divpd, new IntrinsicInfo(X86Instruction.Divpd, IntrinsicType.Binary));
Add(Intrinsic.X86Divps, new IntrinsicInfo(X86Instruction.Divps, IntrinsicType.Binary));
Add(Intrinsic.X86Divsd, new IntrinsicInfo(X86Instruction.Divsd, IntrinsicType.Binary));
diff --git a/ARMeilleure/CodeGen/X86/IntrinsicType.cs b/ARMeilleure/CodeGen/X86/IntrinsicType.cs
index 4e9b33e1..41c52b59 100644
--- a/ARMeilleure/CodeGen/X86/IntrinsicType.cs
+++ b/ARMeilleure/CodeGen/X86/IntrinsicType.cs
@@ -7,6 +7,7 @@ namespace ARMeilleure.CodeGen.X86
Unary,
UnaryToGpr,
Binary,
+ BinaryGpr,
BinaryImm,
Ternary,
TernaryImm
diff --git a/ARMeilleure/CodeGen/X86/X86Instruction.cs b/ARMeilleure/CodeGen/X86/X86Instruction.cs
index a29e68fb..813730f2 100644
--- a/ARMeilleure/CodeGen/X86/X86Instruction.cs
+++ b/ARMeilleure/CodeGen/X86/X86Instruction.cs
@@ -38,6 +38,7 @@ namespace ARMeilleure.CodeGen.X86
Cvtsi2sd,
Cvtsi2ss,
Cvtss2sd,
+ Cvtss2si,
Div,
Divpd,
Divps,